Briefly
I am an assistant professor at the department of Computer Science at Boston University (BU). I received my Ph.D. from the University of Illinois at Urbana-Champaign (UIUC) in 2017. My research focuses on real-time and embedded systems. I am especially interested in partially-reconfigurable platforms and OS-level multi-core resource management technologies for high-performance, safety-critical systems. I am also interested in applications and methodologies to design, deploy and analyze Cyber-Physical Systems (CPS), and in real-time cloud computing. My research also touches on aspects of security for embedded systems and technologies for UAVs.
I am currently looking for motivated master and Ph.D. students who would like to work with me. If you are one those, please contact me! .
Renato MancusoAssistant Professor
Contact me
- Office:
- MCS 211
- Phone:
- +1 (617) 358-8537
- Email:
- rmancuso@bu.edu
- Address:
- 111 Cummington Mall, Boston MA 02215
Updates and News
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Our paper "E-WarP: a System-wide Framework for Memory Bandwidth Profiling and Management" was selected as an outstanding paper at IEEE RTSS'20 . Read the PDF here.
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An article titled "We Have Emphasized Learning and Compassion" appears in the Communications of the ACM and discusses some of my remote teaching phylosophy and approach. Read it online here.
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I am invited to serve as a judge for the BostonHacks competition.
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I am invited to serve on the program committee of DAC'21 for the AS1 Autonomous Systems (Automotive, Robotics, Drones) track.
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Our paper "E-WarP: a System-wide Framework for Memory Bandwidth Profiling and Management" has been accepted to appear at IEEE RTSS'20 . Read the PDF here.
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Our project "Beyond Accelerators - Using FPGAs to Achieve Fine-grained Control of Data-flows in Embedded SoCs" is awarded funding from the National Science Foundation (NSF). See abstract here . Thanks for the support!
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I am invited to serve as web chair for ICCPS'21 .
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I am invited to deliver a keynote speech at the X Brazilian Symposium on Computing Systems Engineering SBESC'20 .
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I am invited to serve as publicity chair for IEEE RTAS'21 .
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I am invited to serve on the program committee of ICPADS'20 in the Architecture Track.
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I am invited to serve on the program committee of DATE'21 for topic E2 "Real-time, dependable and privacy-enhanced systems."
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Our U.S. Patent No. 10649914 "Scratchpad-Based Operating System for Multi-Core Embedded Systems" is officially issued as of May 12, 2020.
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I am invited to serve on the program committee of IEEE RTSS'20 .
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Our paper "The Potential of Programmable Logic in the Middle: Cache Bleaching" has been awarded the best paper award at IEEE RTAS'20. Read the PDF here . The video presentation is available here .
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I am invited to join the committee for this year's ACM Student Research Competition ( SRC ) Grand Finals.
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After weeks of preparation with the editors Heechul Yun & Sophie Quinton, the ACM SIGBED Blog is now live!
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Three projects from my group being presented at the BU Cloud Computing Workshop with IBM and Red Hat. Check out the agenda of the workshop here.
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Our paper "The Potential of Programmable Logic in the Middle: Cache Bleaching" has been accepted to appear in IEEE RTAS'20. Read the PDF here .
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I am invited to serve on the program committee of ACM SIGBED EMSOFT'20 .
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I am organizing the new ACM SIGBED Student Scholars Program. It is open to undergraduate students, giving them the chance to attend CPSWeek 2020 in Sydney at no cost.
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Red Hat made a donation to our group for research on near-memory processing in enterprise systems. Thanks for the support! .
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Bosch GmbH made a donation to our group for research on performance isolation in multi-core automotive systems. Thanks for the support! .
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I will be organizing the 16th annual workshop on Operating Systems Platforms for Embedded Real-Time (OSPERT). Check out the CfP here: OSPERT 2020 .
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I am attending and delivering a talk at 1st Edition of the High-Performance Real-Time Workshop organized by ARM .
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I am invited to serve on the program committee of RTAS'20 .
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I am invited to deliver a talk at WPI as part of the CS colloquium series.
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I am invited to serve on the program committee of DATE'20 .
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I am invited to serve on the program committee of DAC'20 .
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I am joining the Executive Committee of ACM SIGBED as Communication Director .
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I am invited to serve on the program committee of the 7th International Workshop on Mixed Criticality System WMC'19 .
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I will be organizing the first edition of the Student Research Competition (SRC) at ESWEEK this year in New York. The event is supported by ACM and MS Research.
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Our paper "Designing Mixed Criticality Applications onModern Heterogeneous MPSoC Platforms" received the Outstanding Paper Award at ECRTS 2019. Read the PDF here .
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I am invited to serve on the program committee of IEEE RTSS'19 .
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Our paper "Designing Mixed Criticality Applications onModern Heterogeneous MPSoC Platforms" has been accepted to appear in ECRTS 2019. Read the PDF here .
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Our paper "A Real-Time Scratchpad-centric OS with Predictable Inter/Intra-Core Communication for Multi-core Embedded Systems" has been accepted to appear in Real-Time Systems Journal Read the PDF here .
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Our paper "Impact of DM-LRU on WCET: a Static Analysis Approach" has been accepted to appear in ECRTS 2019. Read the PDF here .
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Our paper "Unikernels: The Next Stage of Linux's Dominance" has been accepted to appear in HotOS 2019. Read the PDF here .
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Our project with Prof. Xi Ling (CHEM) on "Data Driven, Inexpensive and Reusable Sensors for Water Contamination Detection" was the recipient for the Hariri Institute Research Incubation Award. Truly grateful for the support!
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I am invited to serve on the program committee of IEEE RTCSA'19 .
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I am invited to serve on the program committee of NENS'19 .
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The preprint for our new work "Neuroflight: Next Generation Flight Control Firmware" is now available on arXiv. Read the PDF here.
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Rolling out new CS-454/654 "Embedded Systems Development" course at BU. This is also the first lab-based course in the CS department. More details here: CS-454/654 Webpage.
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Our paper "Deterministic Memory Hierarchy and Virtualization for Modern Multi-Core Embedded Systems" has been accepted to appear in IEEE RTAS'19. Read the PDF here .
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Our paper "Reinforcement Learning for UAV Attitude Control" has been accepted to appear in ACM Transactions on Cyber-Physical Systems. Read the PDF here .
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I am invited to serve on the program committee of ACM SIGBED EMSOFT'19 .
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I am invited to serve on the program committee of IEEE ICSCC'19 .
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Honored to be an invited speaker at the Technical Fair of Manaus Digital Hub. More info available here .
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Technology transition talk at BU about long-term adoption of multi-core solutions for Industry 4.0.
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Xilinx offers to donate two UltraScale+ MPSoC development kits. Truly grateful for their support.
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Shahin Roozkhosh joined my research group as a Ph.D. student. Welcome on board!
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I am invited to serve on the program committee of IEEE RTAS'19 .
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Our paper "Analysis of Dynamic Memory Bandwidth Regulation in Multi-core Real-Time Systems" has been accepted to appear at IEEE RTSS'18 . Read the PDF here.
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I am invited to serve on the program committee of the brief presentation session at IEEE RTSS'18 .
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I am invited to serve as web chair for IEEE RTAS'19 .
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I am invited to serve on the award selection committee at IEEE RTCSA'18 .
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I am invited to serve on the program committee of the demo session "RTSS@Work" at IEEE RTSS'18 .
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I am invited to serve on the program committee of the "Workshop on Mixed-Criticality" (WMC) at IEEE RTSS'18 .
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Our paper "Evaluating Memory Subsystem of Configurable Heterogeneous MPSoC" has been accepted to appear at OSPERT'18 .
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Our paper "Verification of OS-level Cache Management" has been accepted to appear at OSPERT'18 .
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Honored to be an invited speaker at the "Workshop on Modelling, Measuring and Managing Uncertainty in CPS" at the University of York, UK.
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Our paper "Deterministic Memory Abstraction and Supporting Multicore System Architecture" has been accepted to appear at ECRTS'18 .
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I am invited to serve on the program committee of the "Mixed-Criticality System Design, Implementation and Analysis" Special Session at Euromicro DSD'18 .
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I am invited to serve on the program committee of IEEE RTSS'18 .
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I am invited to serve on the program committee of at IEEE RTCSA'18 .
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I am invited to serve on the program committee of EMSOFT'18 .
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I am invited to serve on the program committee of the WiP session at RTEST'18 .
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I am invited to serve on the program committee of the "Operating Systems Platforms for Embedded Real-Time applications" (OSPERT) workshop at ECRTS'18 .
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I am a co-organizer of the "Second TCRTS Workshop on Certifiable Multicore Avionics and Automotive Systems (CMAAS)". Slides and recordings from the workshop now available here .
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Accepted offer to join the Department of Computer Science at Boston University (BU) as an Assistant Professor starting from Fall 2017.
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Successfully defended my Ph.D. thesis. The PDF is now available here .
Selected Publications
The Potential of Programmable Logic in the Middle: Cache Bleaching – Shahin Roozkhosh, Renato Mancuso
In Proceedings of the 26th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), Sydney, Australia. (Best Paper Award)
Deterministic Memory Hierarchy and Virtualization for Modern Multi-Core Embedded Systems – Tomasz Kloda, Marco Solieri, Renato Mancuso, Nicola Capodieci, Paolo Valente, Marko Bertogna
In Proceedings of the 25th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), Montreal, Canada.
Analysis of Dynamic Memory Bandwidth Regulation in Multi-core Real-Time Systems – Ankit Agrawal, Renato Mancuso, Rodolfo Pellizzoni and Gerhard Fohler
In Proceedings of the 39th IEEE Real-Time Systems Symposium (RTSS 2018), Nashville, TN, USA.
Deterministic Memory Abstraction and Supporting Multicore System Architecture – Farzad Farshchi, Prathap Kumar Valsan, Renato Mancuso, Heechul Yun
In Proceedings of the 30th Euromicro Conference on Real-Time Systems (ECRTS 2018), Barcelona, Spain.
WCET Derivation under Single Core Equivalence with Explicit Memory Budget Assignment – Renato Mancuso, Rodolfo Pellizzoni, Neriman Tokcan, Marco Caccamo
In Proceedings of the 29th Euromicro Conference on Real-Time Systems (ECRTS 2017), Dubrovnik, Croatia.
A Reliable and Predictable OS for Real-Time Embedded Systems – Rohan Tabish, Renato Mancuso, Saud Wasly, Sujit S. Phatak, Rodolfo Pellizzoni, Marco Caccamo
In Proceedings of the 23th IEEE International Conference on Real-Time and Embedded Technology and Applications Symposium (RTAS 2017).
Optimizing Resource Speed for Two-Stage Real-Time Tasks – Alessandra Melani, Renato Mancuso, Daniel Cullina, Marco Caccamo, Lothar Thiele
Real-Time Sytems Journal
Reset-Based Recovery for Real-Time Cyber-Physical Systems with Temporal Safety Constraints – Fardin Abdi, Renato Mancuso, Stanley Bak, Or Dantsker, Marco Caccamo
In Proceedings of the 21st IEEE International Conference on Emerging Technologies Factory Automation and Applications Symposium (ETFA 2016), Berlin, Germany.
A Real-Time Scratchpad-centric OS for Multi-core Embedded Systems – Rohan Tabish, Renato Mancuso, Saud Wasly, Ahmed Alhammad, Sujit S. Phatak, Rodolfo Pellizzoni, Marco Caccamo
best presentation award
In Proceedings of the 22th IEEE International Conference on Real-Time and Embedded Technology and Applications Symposium (RTAS 2016), Vienna, Austria.
Speed Optimization for Tasks with Two Resources – Alessandra Melani, Renato Mancuso, Daniel Cullina, Marco Caccamo, Lothar Thiele
In Proceedings of International Conference on Design, Automation & Test in Europe (DATE). Dresden, Germany.
Single Core Equivalent Virtual Machines for Hard Real-Time Computing on Multicore Processors – Lui Sha, Marco Caccamo, Rodolfo Pellizzoni, Heechul Yun, Renato Mancuso, Jung Eun Kim, Man-Ki Yoon, Russell Kegley, Dennis Perlman, Greg Arundale, Richard Bradford
IEEE Computer Magazine
Using Traffic Phase Shifting to Improve AFDX Link Utilization – Renato Mancuso, Andrew V. Louis, Marco Caccamo
In Proceedings of the 15th ACM International Conference on Embedded and Software (EMSOFT). Amsterdam, The Netherlands
A Memory Access Detection Methodology for Accurate Workload Characterization – Marco Cesati, Renato Mancuso, Emiliano Betti, Marco Caccamo
In Proceedings of the 21th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA). Hong Kong, China
WCET(m) Estimation in Multi-Core Systems using Single Core Equivalence – Renato Mancuso, Rodolfo Pellizzoni, Marco Caccamo, Lui Sha and Heechul Yun
In Proceedings of the 27th Euromicro Conference on Real-Time Systems (ECRTS 2015), Lund, Sweden
A Survey on Cache Management Mechanisms for Predictable Real-Time Embedded Systems – Giovani Gracioli, Ahmed Alhammad, Renato Mancuso, Antonio Augusto Frohlich, Rodolfo Pellizzoni
Accepted for publication on ACM Computing Surveys
Exploiting Structured Human Interactions to Enhance Estimation Accuracy in Cyber-physical Systems – Yunlong Gao, Shaohan Hu, Renato Mancuso, Hongwei Wang, Minje Kim, PoLiang Wu , Lu Su , Lui Sha, Tarek Abdelzaher
In Proceedings of the 6th IEEE International Conference on Cyber-Physical Systems (ICCPS 2015), Seattle, WA, USA
Light-PREM: Automated Software Refactoring for Predictable Execution on COTS Embedded Systems – Renato Mancuso, Roman Dudko, Marco Caccamo
In Proceedings of the 20th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA). Chongqing, China
A Hardware Architecture to Deploy Complex Multiprocessor Scheduling Algorithms – Renato Mancuso, Prakalp Srivastava, Deming Chen, Marco Caccamo
In Proceedings of the 20th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA). Chongqing, China
A Low-Power Architecture for High Frequency Sensor Acquisition in Many-DOF UAVs – Renato Mancuso, Or D. Dantsker, Marco Caccamo, Michael S. Selig
In Proceedings of the 5th IEEE International Conference on Cyber-Physical Systems (ICCPS 2014), Berlin, Germany.
PALLOC: DRAM Bank-Aware Memory Allocator for Performance Isolation on Multicore Platforms – Heechul Yun, Renato Mancuso, Zheng-Pei Wu, Rodolfo Pellizzoni
In Proceedings of the 20th IEEE International Conference on Real-Time and Embedded Technology and Applications Symposium (RTAS 2014), Berlin, Germany.
On-chip Control Flow Integrity Check for Real-Time Embedded Systems – Fardin Abdi Taghi Abad, Joel Van Der Woude, Yi Lu, Stanley Bak, Marco Caccamo, Lui Sha, Renato Mancuso, Sibin Mohan
In Proceedings of the 1st IEEE International Conference on Cyber-Physical Systems, Networks, and Applications (CPSNA 2013), Taipei, Taiwan.
Real-Time Cache Management Framework for Multi-Core Architectures – Renato Mancuso, Roman Dudko, Emiliano Betti, Marco Cesati, Marco Caccamo, Rodolfo Pellizzoni
best student paper award
In Proceedings of the 19th IEEE International Conference on Real-Time and Embedded Technology and Applications Symposium (RTAS 2013), Philadelphia, PA, USA.
Single Core Equivalent Virtual Machines for Hard Real-Time Computing on Multicore Processors – Lui Sha, Marco Caccamo, Renato Mancuso, Jung-Eun Kim, Man-Ki Yoon, Rodolfo Pellizzoni, Heechul Yun, Russel Kegley, Dennis Perlman, Greg Arundale, Richard Bradford
Technical Report at UIUC: PDF here
Response-Time Analysis for Single Core Equivalence Framework – Renato Mancuso, Rodolfo Pellizzoni, Marco Caccamo, Lui Sha, Heechul Yun
Technical Report at UIUC: PDF here
MadT: A Memory Access Detection Tool for Symbolic Memory Profiling – Marco Cesati, Renato Mancuso, Emiliano Betti, Marco Caccamo
Technical Report at UIUC: PDF here
Improving Bandwidth Utilization With Deterministic Delivery Guarantees in AFDX through Traffic Phase-Shifting – Renato Mancuso, Andrew V. Loius, Marco Caccamo
Technical Report at UIUC: PDF here
teaching
education
Bachelor Degree in Computer Engineering
University of Rome "Tor Vergata"
Score: 110/110 summa cum laude
Thesis Title: The Coreboot Project
Advisor: Daniel Pierre Bovet
Master Degree in Computer Engineering
University of Rome "Tor Vergata"
Score: 110/110 summa cum laude
Thesis Title: Avoiding Memory Access Conflicts in Real-Time Multi-Core Systems
Advisor: Marco Cesati
Ph.D. in Computer Science
University of Illinois at Urbana-Champaign
Thesis Title: Next-Generation Safety-Critical Systems on Multi-Core COTS Platforms
Advisor: Marco Caccamo
Honors / Awards
Award: Best Paper Award
Paper title: "The Potential of Programmable
Logic in the Middle: Cache Bleaching"
Conference: 26th IEEE International Conference on Real-Time and Embedded Technology and Applications Symposium (RTAS 2020)
US Patent: Scratchpad-Based Operating System for Multi-Core Embedded Systems
Patent Nr: 10649914
Issued by: University of Illinois at Urbana-Champaign (UIUC)
Inventor(s): Marco Caccamo, Renato Mancuso, Rohan Tabish, Rodolfo Pellizzoni
Status: Pending
Award: Outstanding Paper Award
Paper title: "Designing Mixed Criticality
Applications on Modern Heterogeneous MPSoC
Platforms"
Conference: 31th Euromicro Conference on Real-Time Systems (ECRTS 2019)
Award: Best Presentation Award
Paper title: "A Real-Time Scratchpad-centric
OS for Multi-core Embedded Systems"
Conference: 22th IEEE International Conference on Real-Time and Embedded Technology and Applications Symposium (RTAS 2016)
Fellowship: CS Excellence Fellowship
Description: The Computer Science Excellence
Fellowship is funded thanks to the Graduate
College’s Block Grant Program, which provides funds
to help departments recruit and retain outstanding
graduate students, and thanks to generous donations
to the CS @ ILLINOIS general fellowship
fund.
Issued by: University of Illinois at Urbana-Champaign - Dept. of Computer Science
Award: Best Student Paper Award
Paper title: "Real-Time Cache Management
Framework for Multi-Core Architectures"
Conference: 19th IEEE International Conference on Real-Time and Embedded Technology and Applications Symposium (RTAS 2013)
Patent: Providing Interactive Pharmaceutical Services through Internet
Patent Nr: RM2011A000297
Issued by: CFI PROGETTI S.r.L.
Inventor(s): Renato Mancuso
Status: Issued
Summer School: Nano-Tera/Artist International Summer School
Location: Aix-les-Bains, France
Description: The Nano-Tera/Artist
International Summer School on Embedded System
Design brings together some of the best lecturers
from all over the world in a one week programme.
Over the years it has proven to be a fantastic
opportunity for interaction. We seek a balance
between foundational aspects and applications
embedded software. Speakers include recognized
leading researchers and engineers. The school is
open to PhD students, researchers and
engineers.
Full Merit Scholarship: Collegio Universitario Lamaro-Pozzani
Location: Rome, Italy
Duration: 5 years
Type: Accommodation + Internal Courses
Current Students
This is a list a student that are actively working with me.
Past Students
List of students who graduates under my supervision.
Research skills and expertise
My research involves a mix of skills revolving around operating systems and systems-on-chip. The ratios can be roughly summarized as follows.
Project Overview
A brief overview of the projects in which I am currently involved.
Autonomous Race Car
Research Project We are building a 1/10 scale autonomous race car capable of navigating its surroundings and to perform environment-aware maneuvering. Lear more about this project here: BU Autonomous Race Car.
Scratchpad-Centric OS
Research Project A novel-paradigm real-time operating system (RTOS) designed to achieve strong inter-core performance isolation and to provide strict timing guarantees on scratchpad-based multi-core COTS platforms. The RTOS is based on Erika Enterprise and targets the automotive domain, with special focus on powertrain systems.
Single-Core Equivalence Framework
Research Project A software and theoretical framework to enforce performance isolation on COTS multi-core systems for safety-critical applications, such as avionics and automotive.
Solar UAVs
Research Project In collaboration with UIUC. Design and integration of fixed-wing UAVs capable of real-time sensing and processing from an array of sensors with long-duration flight using solar energy as a primary energy source. Learn more here: Solar UAVs.
Projects
Neuroflight: next-generation flight controller
Neuroflight is the first open source neuro-flight controller software (firmware) for remotely piloting multi-rotors and fixed wing aircraft. Neuroflight's primary focus is to provide optimal flight performance. Neuroflight aims to address limitations in PID control used in Betaflight through the use of neural network flight control (neuro-flight control). Neuro-flight control has been actively researched for more than a decade. In contrast to traditional control algorithms, neuro-flight control has the ability to adapt, plan, and learn. To account for dynamic changes Betaflight has introduced gain scheduling to increase the I gain when certain conditions are met, for example low voltages or high throttle (anti-gravity). On the other hand, neuro-flight control learns the true underlying dynamics of the aircraft allowing for optimal control depending on the current aircraft state. For example neuro-flight control has the potential to learn the batteries discharge rates to dynamically adjust control signal outputs accordingly. The goal of this work is to provide the community with a stable platform to innovate and advance development of neuro-flight control design for drones, and to take a step towards making neuro-flight controllers mainstream. For further details refer to our preprint and please use the following BibTex entry to cite our work,
Single Core Equivalence (SCE)
Much of the real time scheduling for single core chips has centered on the CPU, because it has been the bottleneck resource. The emergence of multicore architectures has moved bottleneck resource away from CPU and towards the now globally shared memory banks, memory controllers, last level cache, and I/O channels. Single Core Equivalent (SCE) is a OS-level software architecture for multicore systems. If managed according to SCE policies, each core can be treated as stand‐alone single-core chip from the point of view of real-time schedulability analysis and certification process. Without a technology like SCE, the change of workload in one core could result in uncontrolled adverse impact on the schedulability of tasks in other cores, triggering the recertification of safety critical applications running in other cores. The time and costs of such recertification is economically unsustainable. This problem is especially critical for the avionic industry. For example, assume that companies A, B, C, D were given IMA partitions in core 1 and their applications were certified. Now, if an application of company E in Core 2 invalidates the schedulability of core 1’s applications, who should do the modification, recertification and pay the bill? Is company E qualified to do the work for companies A, B, C and D? Suppose that Company E pays A, B, C and D to make the changes. What if the modification in Core 1 now invalidates company E’s software schedulability in core 2? Skyrocketing integration costs aside, how can we sort out such circular liability mess?
Scratchpad Centric OS
Multi-core processors have replaced single-core systems in almost every segment of the industry. Unfortunately, their increased complexity often causes a loss of temporal predictability which represents a key requirement for hard real-time systems. Major sources of unpredictability are the shared low level resources, such as the memory hierarchy and the I/O subsystem. With Scratchpad Centric OS, we approach the problem of shared resource arbitration at an OS-level, proposing and implementing a novel design for multi-core platforms revolving around the idea of CPU/memory co-scheduling. In the proposed OS, the predictable usage of shared resources across multiple cores represents a central design-time goal. This project targets scratchpad-based architectures. In this context, we achieve contention-free execution of real-time tasks, while also enforcing a strict separation of application logic and I/O perations in the time domain. To validate the proposed design, we implemented the proposed OS using a commercial-off-the-shelf (COTS) platform. Experiments show that this novel design delivers predictable temporal behavior to hard real-time tasks, and it improves performance up to 2.1x compared to traditional approaches.
Automatic Code Refactoring with Light-PREM
As real-time embedded systems become more complex, there is the need to build them using high performance commercial off-the-shelf (COTS) components. However, tasks can exhibit hard to predict worst case execution times (WCET) when executing on commodity hardware, due to contention among shared physical resources. Past work has introduced the PRedictable Execution Model (PREM) to solve this issue, but unfortunately, the time required to manually refactor existing code according to this model is too high. Light-PREM proposes a novel technique that automates the refactoring process needed to convert legacy software applications to PREM-compliant code. The advantage of Light-PREM is twofold. On one side, it makes the adoption of PREM more attractive from an industrial point of view, because it significantly reduces the amount of work that is needed to generate PREM-compliant code. On the other hand, the proposed methodology is general enough to be used with any embedded software design. Experimental results show that Light-PREM significantly improves the predictability of real-time applications without requiring software engineers to gain a deep understanding about software memory usage.
A Fast, Lightwight and Versatile Data Acquisition System for UAVs
In this project, we developed a high-frequency sensor data acquisition system (SDAC) for flight control and aerodynamic data collection research on small to mid-sized unmanned aerial vehicles (UAVs). The system is both low weight and low power, operates at 100 Hz and features: a high-frequency, high-resolution six degree-offreedom (6-DOF) inertial measurement unit (IMU) with a global positioning system (GPS) receiver, a 3-axis magnetometer, a pitot probe, seven 10-bit analog-to-digital converters (ADC), sixteen 12-bit analog-to-digital converters, a 14-bit analog-to-digital converter, twenty digital input/outputs (I/O), eight pulse width modulation (PWM) signal inputs, a 40 mile downlink transceiver, an open serial and an open CANbus port, and up to 64 GB of onboard storage. The data acquisition system was completely fabricated from commercial-off-theshelf (COTS) components, which reduced the system cost and implementation time. The SDAC combines the large variety of sensor streams into a unified high-fidelity state data stream that is recorded for later aerodynamics analysis and simultaneously forwarded to a separate processing unit, such as an autopilot.
Ground Station and UAV Tracking System
A custom UAV tracking system was implemented on the ground station interface to display sensor and state data and transmit commands to the aircraft instrumentation. The system was designed to provide the human pilot with a quick view of the state of the aircraft. The interface has five sub-displays that show: the physical state of the aircraft, the control inputs, the location of the aircraft; a primary flight display; and a raw input data feed. Along with the displays, the interface has input buttons to start and stop onboard logging and make adjustments to the sub-displays. The system was implemented such that all the aircraft specific data is input into a configuration file, thereby not requiring any modifications to the code to go from aircraft to aircraft. The graphical user interface, which was implemented in a 16:9 ratio to be displayed on today’s high resolution monitors, can be seen in action in the video below.
Hardware Scheduler + PicOS
An increasing demand for high-performance systems has been observed in the domain of both general purpose and real-time systems, pushing the industry towards a pervasive transition to multi-core platforms. Unfortunately, well-known and efficient scheduling results for single-core systems do not scale well to the multi-core domain. This justifies the adoption of more computationally intensive algorithms, but the complexity and computational overhead of these algorithms impact their applicability to real OSes. We studied and implemented an architecture to migrate the burden of multi-core scheduling to a dedicated hardware component. We show that it is possible to mitigate the overhead of complex algorithms, while achieving power efficiency and optimizing processors utilization. We develop the idea of 'active monitoring' to continuously track the evolution of scheduling parameters as tasks execute on processors. This allows reducing the gap between implementable scheduling techniques and the ideal fluid scheduling model, under the constraints of realistic hardware.
Restartable Software/Hardware Architecture
In traditional computing systems, software problems are often resolved by platform restarts. This approach, however, cannot be naïvely used in cyberphysical systems (CPS). In fact, in this class of systems, ensuring safety strictly depends on the ability to respect hard real-time constraints. Several adaptations of the Simplex architecture have been proposed to guarantee safety in spite of misbehaving software components. However, the problem of performing recovery into a fully operational state has not been extensively addressed. We studied how resets can be used in CPS as an effective strategy to recover from a variety of software faults. Our work extends the Simplex architecture in a number of directions. First, we provide sufficient conditions under which safety is guaranteed in spite of fault-induced resets. Second, we introduce a novel technique to express not only state-dependent safety constraints, as typically done in Simplex, but also time-dependent safety properties. Finally, through a proof-of-concept minimal implementation on a small R/C helicopter and simulation-based system modeling, we show the effectiveness of the proposed recovery strategy under the assumed fault model.
Other Projects
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Strong from a 15-year combined expertise in the development of research- and industry-grade solutions for high-accuracy flight data acquisition, our technology is now commercially available. With Al Volo we propose a line of plug&play, power-efficient, lightweight, compact and flexible Flight Data Acquisition (FDAQ) systems. Our FDAQs are able to acquire calibrated sensor with sample rates up to 400 Hz, and support a range of commercial IMUs, differential GPS, integration with external autopilots, internal data logging, integrated high-power radio link, and an always-ready mobile-friendly configuration interface. Discover more about Al Volo FDAQs here and get in touch with us to learn more about how to integrate our solutions in your next UAV project.
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As a native speaker of the Sicilian language I have been lucky enough to be invited to Chair the Cadèmia Siciliana Sicilian Language Technology Committee. During my time on the committee we've been extremely successful in advancing Sicilian language in technology. We've submitted Sicilian to Unicode's CLDR database, watched as YouTube, Android, and Facebook have replied to our requests to have Sicilian included, and we've made rapid progress on translating Firefox into Sicilian. Our first two years at Cadèmia have been great for both Sicilian and regional and minority rights on the internet in general. Hopefully we can continue to build bridges between a love for our mother tongue and technology!
Online Resources
travels
Random shots from places where I have been