I am an assistant professor at the department of Computer Science at Boston University (BU). I received my Ph.D. from the University of Illinois at Urbana-Champaign (UIUC) in 2017. My research focuses on real-time and embedded systems. I am especially interested in partially-reconfigurable platforms and OS-level multi-core resource management technologies for high-performance, safety-critical systems. I am also interested in applications and methodologies to design, deploy and analyze Cyber-Physical Systems (CPS), and in real-time cloud computing. My research also touches on aspects of security for embedded systems and technologies for UAVs.
I am currently looking for motivated master and Ph.D. students who would like to work with me. If you are one those, please contact me! .
In Proceedings of the 41st IEEE Real-Time Systems Symposium (RTSS), Houston, TX, USA (Online). (Best Student Paper Award)
In Proceedings of the 26th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), Sydney, Australia. (Best Paper Award)
In Proceedings of the 25th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), Montreal, Canada.
In Proceedings of the 39th IEEE Real-Time Systems Symposium (RTSS 2018), Nashville, TN, USA.
In Proceedings of the 30th Euromicro Conference on Real-Time Systems (ECRTS 2018), Barcelona, Spain.
In Proceedings of the 29th Euromicro Conference on Real-Time Systems (ECRTS 2017), Dubrovnik, Croatia.
In Proceedings of the 23th IEEE International Conference on Real-Time and Embedded Technology and Applications Symposium (RTAS 2017).
Real-Time Sytems Journal
In Proceedings of the 21st IEEE International Conference on Emerging Technologies Factory Automation and Applications Symposium (ETFA 2016), Berlin, Germany.
best presentation award
In Proceedings of the 22th IEEE International Conference on Real-Time and Embedded Technology and Applications Symposium (RTAS 2016), Vienna, Austria.
In Proceedings of International Conference on Design, Automation & Test in Europe (DATE). Dresden, Germany.
IEEE Computer Magazine
In Proceedings of the 15th ACM International Conference on Embedded and Software (EMSOFT). Amsterdam, The Netherlands
In Proceedings of the 21th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA). Hong Kong, China
In Proceedings of the 27th Euromicro Conference on Real-Time Systems (ECRTS 2015), Lund, Sweden
Accepted for publication on ACM Computing Surveys
In Proceedings of the 6th IEEE International Conference on Cyber-Physical Systems (ICCPS 2015), Seattle, WA, USA
In Proceedings of the 20th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA). Chongqing, China
In Proceedings of the 20th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA). Chongqing, China
In Proceedings of the 5th IEEE International Conference on Cyber-Physical Systems (ICCPS 2014), Berlin, Germany.
In Proceedings of the 20th IEEE International Conference on Real-Time and Embedded Technology and Applications Symposium (RTAS 2014), Berlin, Germany.
In Proceedings of the 1st IEEE International Conference on Cyber-Physical Systems, Networks, and Applications (CPSNA 2013), Taipei, Taiwan.
best student paper award
In Proceedings of the 19th IEEE International Conference on Real-Time and Embedded Technology and Applications Symposium (RTAS 2013), Philadelphia, PA, USA.
Technical Report at UIUC: PDF here
Technical Report at UIUC: PDF here
Technical Report at UIUC: PDF here
Technical Report at UIUC: PDF here
Score: 110/110 summa cum laude
Thesis Title: The Coreboot Project
Advisor: Daniel Pierre Bovet
Score: 110/110 summa cum laude
Thesis Title: Avoiding Memory Access Conflicts in Real-Time Multi-Core Systems
Advisor: Marco Cesati
Thesis Title: Next-Generation Safety-Critical Systems on Multi-Core COTS Platforms
Advisor: Marco Caccamo
Conference: 26th IEEE International Conference on Real-Time and Embedded Technology and Applications Symposium (RTAS 2020)
Issued by: University of Illinois at Urbana-Champaign (UIUC)
Inventor(s): Marco Caccamo, Renato Mancuso, Rohan Tabish, Rodolfo Pellizzoni
Status: Pending
Conference: 31th Euromicro Conference on Real-Time Systems (ECRTS 2019)
Conference: 22th IEEE International Conference on Real-Time and Embedded Technology and Applications Symposium (RTAS 2016)
Issued by: University of Illinois at Urbana-Champaign - Dept. of Computer Science
Conference: 19th IEEE International Conference on Real-Time and Embedded Technology and Applications Symposium (RTAS 2013)
Issued by: CFI PROGETTI S.r.L.
Inventor(s): Renato Mancuso
Status: Issued
Duration: 5 years
Type: Accommodation + Internal Courses
This is a list a student that are actively working with me.
List of students who graduates under my supervision.
My research involves a mix of skills revolving around operating systems and systems-on-chip. The ratios can be roughly summarized as follows.
A brief overview of the projects in which I am currently involved.
Neuroflight is the first open source neuro-flight controller software (firmware) for remotely piloting multi-rotors and fixed wing aircraft. Neuroflight's primary focus is to provide optimal flight performance. Neuroflight aims to address limitations in PID control used in Betaflight through the use of neural network flight control (neuro-flight control). Neuro-flight control has been actively researched for more than a decade. In contrast to traditional control algorithms, neuro-flight control has the ability to adapt, plan, and learn. To account for dynamic changes Betaflight has introduced gain scheduling to increase the I gain when certain conditions are met, for example low voltages or high throttle (anti-gravity). On the other hand, neuro-flight control learns the true underlying dynamics of the aircraft allowing for optimal control depending on the current aircraft state. For example neuro-flight control has the potential to learn the batteries discharge rates to dynamically adjust control signal outputs accordingly. The goal of this work is to provide the community with a stable platform to innovate and advance development of neuro-flight control design for drones, and to take a step towards making neuro-flight controllers mainstream. For further details refer to our preprint and please use the following BibTex entry to cite our work,
Much of the real time scheduling for single core chips has centered on the CPU, because it has been the bottleneck resource. The emergence of multicore architectures has moved bottleneck resource away from CPU and towards the now globally shared memory banks, memory controllers, last level cache, and I/O channels. Single Core Equivalent (SCE) is a OS-level software architecture for multicore systems. If managed according to SCE policies, each core can be treated as stand‐alone single-core chip from the point of view of real-time schedulability analysis and certification process. Without a technology like SCE, the change of workload in one core could result in uncontrolled adverse impact on the schedulability of tasks in other cores, triggering the recertification of safety critical applications running in other cores. The time and costs of such recertification is economically unsustainable. This problem is especially critical for the avionic industry. For example, assume that companies A, B, C, D were given IMA partitions in core 1 and their applications were certified. Now, if an application of company E in Core 2 invalidates the schedulability of core 1’s applications, who should do the modification, recertification and pay the bill? Is company E qualified to do the work for companies A, B, C and D? Suppose that Company E pays A, B, C and D to make the changes. What if the modification in Core 1 now invalidates company E’s software schedulability in core 2? Skyrocketing integration costs aside, how can we sort out such circular liability mess?
Multi-core processors have replaced single-core systems in almost every segment of the industry. Unfortunately, their increased complexity often causes a loss of temporal predictability which represents a key requirement for hard real-time systems. Major sources of unpredictability are the shared low level resources, such as the memory hierarchy and the I/O subsystem. With Scratchpad Centric OS, we approach the problem of shared resource arbitration at an OS-level, proposing and implementing a novel design for multi-core platforms revolving around the idea of CPU/memory co-scheduling. In the proposed OS, the predictable usage of shared resources across multiple cores represents a central design-time goal. This project targets scratchpad-based architectures. In this context, we achieve contention-free execution of real-time tasks, while also enforcing a strict separation of application logic and I/O perations in the time domain. To validate the proposed design, we implemented the proposed OS using a commercial-off-the-shelf (COTS) platform. Experiments show that this novel design delivers predictable temporal behavior to hard real-time tasks, and it improves performance up to 2.1x compared to traditional approaches.
As real-time embedded systems become more complex, there is the need to build them using high performance commercial off-the-shelf (COTS) components. However, tasks can exhibit hard to predict worst case execution times (WCET) when executing on commodity hardware, due to contention among shared physical resources. Past work has introduced the PRedictable Execution Model (PREM) to solve this issue, but unfortunately, the time required to manually refactor existing code according to this model is too high. Light-PREM proposes a novel technique that automates the refactoring process needed to convert legacy software applications to PREM-compliant code. The advantage of Light-PREM is twofold. On one side, it makes the adoption of PREM more attractive from an industrial point of view, because it significantly reduces the amount of work that is needed to generate PREM-compliant code. On the other hand, the proposed methodology is general enough to be used with any embedded software design. Experimental results show that Light-PREM significantly improves the predictability of real-time applications without requiring software engineers to gain a deep understanding about software memory usage.
In this project, we developed a high-frequency sensor data acquisition system (SDAC) for flight control and aerodynamic data collection research on small to mid-sized unmanned aerial vehicles (UAVs). The system is both low weight and low power, operates at 100 Hz and features: a high-frequency, high-resolution six degree-offreedom (6-DOF) inertial measurement unit (IMU) with a global positioning system (GPS) receiver, a 3-axis magnetometer, a pitot probe, seven 10-bit analog-to-digital converters (ADC), sixteen 12-bit analog-to-digital converters, a 14-bit analog-to-digital converter, twenty digital input/outputs (I/O), eight pulse width modulation (PWM) signal inputs, a 40 mile downlink transceiver, an open serial and an open CANbus port, and up to 64 GB of onboard storage. The data acquisition system was completely fabricated from commercial-off-theshelf (COTS) components, which reduced the system cost and implementation time. The SDAC combines the large variety of sensor streams into a unified high-fidelity state data stream that is recorded for later aerodynamics analysis and simultaneously forwarded to a separate processing unit, such as an autopilot.
A custom UAV tracking system was implemented on the ground station interface to display sensor and state data and transmit commands to the aircraft instrumentation. The system was designed to provide the human pilot with a quick view of the state of the aircraft. The interface has five sub-displays that show: the physical state of the aircraft, the control inputs, the location of the aircraft; a primary flight display; and a raw input data feed. Along with the displays, the interface has input buttons to start and stop onboard logging and make adjustments to the sub-displays. The system was implemented such that all the aircraft specific data is input into a configuration file, thereby not requiring any modifications to the code to go from aircraft to aircraft. The graphical user interface, which was implemented in a 16:9 ratio to be displayed on today’s high resolution monitors, can be seen in action in the video below.
An increasing demand for high-performance systems has been observed in the domain of both general purpose and real-time systems, pushing the industry towards a pervasive transition to multi-core platforms. Unfortunately, well-known and efficient scheduling results for single-core systems do not scale well to the multi-core domain. This justifies the adoption of more computationally intensive algorithms, but the complexity and computational overhead of these algorithms impact their applicability to real OSes. We studied and implemented an architecture to migrate the burden of multi-core scheduling to a dedicated hardware component. We show that it is possible to mitigate the overhead of complex algorithms, while achieving power efficiency and optimizing processors utilization. We develop the idea of 'active monitoring' to continuously track the evolution of scheduling parameters as tasks execute on processors. This allows reducing the gap between implementable scheduling techniques and the ideal fluid scheduling model, under the constraints of realistic hardware.
In traditional computing systems, software problems are often resolved by platform restarts. This approach, however, cannot be naïvely used in cyberphysical systems (CPS). In fact, in this class of systems, ensuring safety strictly depends on the ability to respect hard real-time constraints. Several adaptations of the Simplex architecture have been proposed to guarantee safety in spite of misbehaving software components. However, the problem of performing recovery into a fully operational state has not been extensively addressed. We studied how resets can be used in CPS as an effective strategy to recover from a variety of software faults. Our work extends the Simplex architecture in a number of directions. First, we provide sufficient conditions under which safety is guaranteed in spite of fault-induced resets. Second, we introduce a novel technique to express not only state-dependent safety constraints, as typically done in Simplex, but also time-dependent safety properties. Finally, through a proof-of-concept minimal implementation on a small R/C helicopter and simulation-based system modeling, we show the effectiveness of the proposed recovery strategy under the assumed fault model.
Random shots from places where I have been