@article{XStream_JSYS23,
title = {X-Stream: Accelerating streaming segments on MPSoCs for
real-time applications},
journal = {Journal of Systems Architecture},
pages = {102857},
year = {2023},
issn = {1383-7621},
doi = {https://doi.org/10.1016/j.sysarc.2023.102857},
author = {Tabish, Rohan and Pellizzoni, Rodolfo and Mancuso, Renato and Gracioli, Giovani and Mirosanlou, Reza and Caccamo, Marco},
keywords = {MPSoC, Segment streaming, Heterogeneous computing},
abstract = {We are witnessing a race to meet the ever-growing
computation requirements of emerging AI applications
to provide perception and control in autonomous
vehicles — e.g., self-driving cars and UAVs. To
remain competitive, vendors are packing more
processing units (CPUs, programmable logic, GPUs,
and hardware accelerators) into next-generation
multiprocessor systems-on-a-chip (MPSoC). As a
result, modern embedded platforms are achieving new
heights in peak computational
capacity. Unfortunately, however, the collateral and
inevitable increase in complexity represents a major
obstacle for the development of correct-by-design
safety-critical real-time applications. Due to the
ever-growing gap between fast-paced hardware
evolution and comparatively slower evolution of
real-time operating systems (RTOS), there is a need
for real-time oriented full-platform management
frameworks to complement traditional RTOS
designs. In this work, we propose one such
framework, namely the X-Stream framework, for the
definition, synthesis, and analysis of real-time
workloads targeting state-of-the-art
accelerator-augmented embedded platforms. Our
X-Stream framework is designed around two cardinal
principles. First, computation and data movements
are orchestrated to achieve predictability by
design. For this purpose, iterative computation over
large data chunks is divided into subsequent
segments. These segments are then streamed
leveraging the three-phase execution model (load,
execute and unload). Second, the framework is
workflow-centric: system designers can specify their
workflow and the necessary code for workflow
orchestration is automatically generated. In
addition to automating the deployment of
user-defined hardware-accelerated workloads,
X-Stream supports the deployment of some computation
segments on traditional CPUs. Finally, X-Stream
allows the definition of real-time partitions. Each
partition groups applications belonging to the same
criticality level and that share the same set of
hardware resources, with support for preemptive
priority-driven scheduling. Conversely, freedom from
interference for applications deployed in different
partitions is guaranteed by design. We provide a
full-system implementation that includes RTOS
integration and showcase the proposed X-Stream
framework on a Xilinx Ultrascale+ platform by
focusing on a matrix-multiplication and addition
kernel use-case.}
type = {journal},
durl = {files/papers/XStream_JSYS23.pdf}
}

@article{LazyLoad_TECS23,
author = {Kloda, Tomasz and Gracioli, Giovani and Tabish, Rohan and
Mirosanlou, Reza and Mancuso, Renato and Pellizzoni,
Rodolfo and Caccamo, Marco},
title = {Lazy Load Scheduling for Mixed-Criticality Applications in
Heterogeneous MPSoCs},
year = {2023},
publisher = {Association for Computing Machinery},
address = {New York, NY, USA},
issn = {1539-9087},
doi = {10.1145/3587694},
abstract = {Newly emerging multiprocessor system-on-a-chip (MPSoC)
platforms provide hard processing cores with
programmable logic (PL) for high-performance
computing applications. In this paper, we take a
deep look into these commercially available
heterogeneous platforms and show how to design
mixed-criticality applications such that different
processing components can be isolated to avoid
contention on the shared resources such as
last-level cache and main memory. Our approach
involves software/hardware co-design to achieve
isolation between the different criticality
domains. At the hardware level, we use a scratchpad
memory (SPM) with dedicated interfaces inside the PL
to avoid conflicts in the main memory. Whereas, at
the software level, we employ a hypervisor to
support cache-coloring such that conflicts at the
shared L2 cache can be avoided. In order to move the
tasks in/out of the SPM memory, we rely on a DMA
engine and propose a new CPU-DMA co-scheduling
policy, called Lazy Load, for which we also derive
the response time analysis. The results of a case
study on image processing demonstrate that the
contention on the shared memory subsystem can be
avoided when running with our proposed
architecture. Moreover, comprehensive schedulability
evaluations show that the newly proposed Lazy Load
policy outperforms the existing CPU-DMA scheduling
approaches and is effective in mitigating the main
memory interference in our proposed architecture.},
journal = {ACM Trans. Embed. Comput. Syst.},
month = {mar},
keywords = {Mixed-criticality real-time systems, schedulability
analysis., heterogeneous multiprocessor
systems-on-chip}
type = {journal},
durl = {files/papers/LazyLoad_TECS23.pdf}
}

@inproceedings{profile_QoS_RTSJ22,
title = {Profile-driven memory bandwidth management for accelerators and CPUs in QoS-enabled platforms},
author       = {Sohal, Parul and Tabish, Rohan and Drepper, Ulrich and Mancuso, Renato},
year         = 2022,
month        = {Dec.},
journal      = {Real-Time Systems},
publisher    = {Springer},
issn         = {1573-1383},
doi          = {https://doi.org/10.1007/s11241-022-09382-x},
type         = {journal}
durl         = {files/papers/ProfileDriven_RTSJ22.pdf}
}

@article{cacheflow_tc21,
title        = {
{Observing the Invisible: Live Cache Inspection for High-Performance
Embedded Systems}
},
author       = {Tarapore, Dharmesh and Roozkhosh, Shahin and Brzozowski, Steven and Mancuso, Renato},
year         = 2022,
month        = {March},
address = {Los Alamitos, CA, USA},
issn = {1557-9956},
journal      = {IEEE Transactions on Computers},
volume       = {71},
number       = {03},
pages        = {559--572},
issn = {1557-9956},
doi          = {10.1109/TC.2021.3060650},
type         = {journal},
durl         = {files/papers/CacheFlow_IEEE_TC21.pdf}
}

@article{TABISH2021102178,
title        = {
{An analyzable inter-core communication framework for high-performance
multicore embedded systems}
},
author       = {
Tabish, Rohan and Wen, Jen-Yang and Pellizzoni, Rodolfo and Mancuso, Renato and Yun, Heechul and Caccamo, Marco and Sha, Lui
},
year         = 2021,
journal      = {Journal of Systems Architecture},
pages        = 102178,
doi          = {https://doi.org/10.1016/j.sysarc.2021.102178},
issn         = {1383-7621},
url          = {https://www.sciencedirect.com/science/article/pii/S1383762121001284},
keywords     = {
High-performance computing, Communication, Inter-core, Multicore,
Heterogeneous systems, Embedded systems
},
abstract     = {
Multicore processors provide great average-case performance. However, the
use of multicore processors for safety-critical applications can lead to
catastrophic consequences because of contention on shared resources. The
problem has been well-studied in literature, and solutions such as
partitioning of shared resources have been proposed. Strict partitioning of
memory resources among cores, however, does not allow intercore
communication. This paper proposes a Communication Core Model (CCM) that
implements the inter-core communication by bounding the amount of intercore
interference in a partitioned multicore system. A system-level perspective
of how to realize such CCM along with the implementation details is
provided. A formula to derive the WCET of the tasks using CCM is provided.
We compare our proposed CCM with Contention-based Communication (CBC),
where no private banking is enforced for any core. The analytical approach
results using San Diego Vision Benchmark Suite (SD-VBS) for two models
indicate that the CCM shows an improvement of up to 65 percent compared to
the CBC. Moreover, our experimental results indicate that the measured WCET
using SD-VBS is within the bounds calculated using the proposed analysis.
},
type         = {journal},
durl         = {files/papers/SCEComm_JSYS21.pdf}
}

@article{SmoothUAVCtrl_TCPS21,
title        = {
{How to Train your Quadrotor: A Framework for Consistently Smooth and
Responsive Flight Control via Reinforcement Learning}
},
author       = {Mysore, Siddharth and El Mabsout, Bassel and Saenko, Kate and Mancuso, Renato},
year         = 2021,
journal      = {ACM Transactions on Cyber-Physical Systems},
publisher    = {ACM},
address      = {New York, NY, USA},
keywords     = {
Attitude control, PID, UAV, adaptive control, autopilot, intelligent
control, machine learning, quadcopter, reinforcement learning
},
type         = {journal},
durl         = {https://arxiv.org/pdf/2012.06656}
}

@article{UAV_att_rl,
title        = {{Reinforcement Learning for UAV Attitude Control}},
author       = {Koch, William and Mancuso, Renato and West, Richard and Bestavros, Azer},
year         = 2019,
month        = feb,
journal      = {ACM Transactions on Cyber-Physical Systems},
publisher    = {ACM},
address      = {New York, NY, USA},
volume       = 3,
number       = 2,
pages        = {22:1--22:21},
doi          = {10.1145/3301273},
issn         = {2378-962X},
url          = {http://doi.acm.org/10.1145/3301273},
issue_date   = {March 2019},
articleno    = 22,
numpages     = 21,
acmid        = 3301273,
keywords     = {
Attitude control, PID, UAV, adaptive control, autopilot, intelligent
control, machine learning, quadcopter, reinforcement learning
},
type         = {journal},
durl         = {https://arxiv.org/pdf/1804.04154}
}

@article{spm_os_journal,
title        = {
{A Real-Time Scratchpad-centric OS with Predictable Inter/Intra-Core
Communication for Multi-core Embedded Systems}
},
author       = {
Tabish, Rohan and Mancuso, Renato and Wasly, Saud and Pellizzoni, Rodolfo and Caccamo, Marco
},
year         = 2019,
month        = {Oct.},
day          = 1,
journal      = {Real-Time Systems},
publisher    = {Springer Netherlands},
volume       = 55,
number       = 4,
pages        = {850--888},
doi          = {10.1007/s11241-019-09340-0},
issn         = {0922-6443},
abstract     = {
Multi-core processors have replaced single-core systems in almost every
segment of the industry. Unfortunately, their increased complexity often
causes a loss of temporal predictability which represents a key requirement
for hard real-time systems. Major sources of unpredictability are shared
low level resources, such as the memory hierarchy and the I/O subsystem. In
this paper, we approach the problem of shared resource arbitration at an
OS-level and propose a novel scratchpad-centric OS design for multi-core
platforms. In the proposed OS, the predictable usage of shared resources
across multiple cores represents a central design-time goal. Hence, we show
(i) how contention-free execution of real-time tasks can be achieved on
scratchpad-based architectures, and (ii) how a separation of application
logic and I/O operations in time domain can be enforced, and (iii) how
predictable asynchronous inter/intra-core communication between tasks can
be performed. To validate the proposed design, we implemented the proposed
OS using commercial-off-the-shelf (MPC5777M) platform. Experimental results
show that novel design delivers predictable temporal behavior to hard
real-time tasks, and it provides performance gain of upto 2.1× compared to
traditional approaches.
},
language     = {English (US)},
type         = {journal},
durl         = {files/papers/SPM-OS_RTSJ19.pdf}
}

@article{melani2017optimizing,
title        = {{Optimizing resource speed for two-stage real-time tasks}},
author       = {
Melani, Alessandra and Mancuso, Renato and Cullina, Daniel and Caccamo,
Marco and Thiele, Lothar
},
year         = 2017,
journal      = {Real-Time Systems},
publisher    = {Springer Netherlands},
volume       = 53,
number       = 1,
pages        = {82--120},
doi          = {10.1007/s11241-016-9259-y},
type         = {journal},
durl         = {files/papers/flowshow_rtsj17.pdf}
}

@article{Wang17,
title        = {
{On Exploiting Structured Human Interactions to Enhance Sensing Accuracy in
Cyber-physical Systems}
},
author       = {
Wang, Hongwei and Gao, Yunlong and Hu, Shaohan and Wang, Shiguang and Mancuso, Renato and Kim, Minje
and Wu, Poliang and Su, Lu and Sha, Lui and Abdelzaher, Tarek
},
year         = 2017,
month        = jul,
journal      = {ACM Trans. Cyber-Phys. Syst.},
publisher    = {ACM},
address      = {New York, NY, USA},
volume       = 1,
number       = 3,
pages        = {16:1--16:19},
doi          = {10.1145/3064006},
issn         = {2378-962X},
url          = {http://doi.acm.org/10.1145/3064006},
issue_date   = {July 2017},
articleno    = 16,
numpages     = 19,
type         = {journal},
acmid        = 3064006,
keywords     = {Workflow, medical, sensing},
type         = {journal},
durl         = {files/papers/struct_int_TCPS17.pdf}
}

@article{7562325,
title        = {{Real-Time Computing on Multicore Processors}},
author       = {Sha, Lui and Caccamo, Marco and Mancuso, Renato and Kim, Jung-Eun and Yoon, Man-Ki and Pellizzoni, Rodolfo and Yun, Heechul and Kegley, Russel B. and Perlman, Dennis R. and Arundale, Greg and Bradford, Richard},
year         = 2016,
month        = {Sept},
journal      = {IEEE Computer},
volume       = 49,
number       = 9,
pages        = {69--77},
doi          = {10.1109/MC.2016.271},
issn         = {0018-9162},
type         = {journal},
abstract     = {
Architects of multicore chips for avionics must define and bound intercore
interference, which requires assuming a constant worst-case execution time
for tasks executing on the chip. With the Single Core Equivalent technology
package, engineers can treat each core as if it were a single-core chip.
},
keywords     = {
avionics;microprocessor chips;multiprocessing systems;real-time
systems;avionics;constant worst-case execution time;intercore
interference;multicore chips;multicore processors;real-time
computing;single-core chip;single-core equivalent technology package;Memory
access;Multicore processing;Real-time systems;Single core
equivalence;avionics computing;memory-access conflicts;multicore
architecture;multicore chips;multicore processing;real-time
systems;single-core equivalence
},
durl         = {files/papers/IEEE_Comp_SCE.pdf},
slides       = {files/slides/SCE_Slides/}
}

@article{gracioli2015survey,
title        = {{A Survey on Cache Management Mechanisms for Real-Time Embedded Systems}},
author       = {
Gracioli, Giovani and Alhammad, Ahmed and Mancuso, Renato and Fr\"{o}hlich,
Ant\^{o}nio Augusto and Pellizzoni, Rodolfo
},
year         = 2015,
month        = {Nov.},
journal      = {ACM Comput. Surv.},
publisher    = {ACM},
address      = {New York, NY, USA},
volume       = 48,
number       = 2,
pages        = {32:1--32:36},
doi          = {10.1145/2830555},
issn         = {0360-0300},
url          = {https://doi.org/10.1145/2830555},
issue_date   = {November 2015},
articleno    = {Article 32},
numpages     = 36,
keywords     = {
memory allocators, compilers, cache partitioning, cache locking, Real-time
systems
},
type         = {journal},
durl         = {files/papers/cache_survey_CSUR15.pdf}
}

@inproceedings{LiveTPA_ECRTS23,
title        = {{Low-overhead Online Assessment of Timely Progress
as a System Commodity}},
author       = {Chen, Weifan and Izhbirdeev, Ivan and Hoornaert, Denis and Roozkhosh, Shahin and Carpanedo, Patrick and Sharma, Sanskriti and Mancuso, Renato},
year         = 2023,
month        = {July},
booktitle    = {35th Euromicro Conference on Real-Time Systems (ECRTS 2023)},
pages =	{13:1--13:26},
series =	{Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN =	{978-3-95977-280-8},
ISSN =	{1868-8969},
volume =	{262},
editor =	{Papadopoulos, Alessandro V.},
publisher    = {Schloss Dagstuhl--Leibniz-Zentrum fuer Informatik},
address      = {Vienna, Austria},
type         = {conference},
remark       = {Outstanding Paper Award, Best Presentation Award},
durl         = {files/papers/LiveTPA_ECRTS23.pdf}
}

@inproceedings{DistributionRegulation_ECRTS23,
title        = {
{Memory Latency Distribution-Driven Regulation for Temporal Isolation in MPSoCs}
},
author       = {Saeed, Ahsan and Hoornaert, Denis and Dasari, Dakshina and Ziegenbein, Dirk and Mueller-Gritschneder, Daniel and Schlichtmann, Ulf and Gerstlauer, Andreas and Mancuso, Renato},
year         = 2023,
month        = {July},
booktitle    = {35th Euromicro Conference on Real-Time Systems (ECRTS 2023)},
pages =	{4:1--4:23},
series =	{Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN =	{978-3-95977-280-8},
ISSN =	{1868-8969},
volume =	{262},
editor =	{Papadopoulos, Alessandro V.},
publisher    = {Schloss Dagstuhl--Leibniz-Zentrum fuer Informatik},
address      = {Vienna, Austria},
type         = {conference},
remark       = {Outstanding Paper Award},
durl         = {files/papers/DistributionRegulation_ECRTS23.pdf}
}

@inproceedings{10.1145/3552326.3587458,
author = {Raza, Ali and Unger, Thomas and Boyd, Matthew and Munson, Eric B and Sohal, Parul and Drepper, Ulrich and Jones, Richard and De Oliveira, Daniel Bristot and Woodman, Larry and Mancuso, Renato and Appavoo, Jonathan and Krieger, Orran},
title = {Unikernel Linux (UKL)},
year = {2023},
isbn = {9781450394871},
publisher = {Association for Computing Machinery},
address = {New York, NY, USA},
url = {https://doi.org/10.1145/3552326.3587458},
doi = {10.1145/3552326.3587458},
abstract = {This paper presents Unikernel Linux (UKL), a path toward integrating unikernel optimization techniques in Linux, a general purpose operating system. UKL adds a configuration option to Linux allowing for a single, optimized process to link with the kernel directly, and run at supervisor privilege. This UKL process does not require application source code modification, only a re-link with our, slightly modified, Linux kernel and glibc. Unmodified applications show modest performance gains out of the box, and developers can further optimize applications for more significant gains (e.g. 26\% throughput improvement for Redis). UKL retains support for co-running multiple user level processes capable of communicating with the UKL process using standard IPC. UKL preserves Linux`s battle-tested codebase, community, and ecosystem of tools, applications, and hardware support. UKL runs both on bare-metal and virtual servers and supports multi-core execution. The changes to the Linux kernel are modest (1250 LOC).},
booktitle = {18th European Conference on Computer Systems (EuroSys 2023)},
pages = {590–605},
numpages = {16},
month = {may},
keywords = {unikernels, specialized operating systems, linux},
location = {Rome, Italy},
series = {EuroSys `23},
type         = {conference},
durl         = {https://arxiv.org/pdf/2206.00789.pdf}
}

@inproceedings{SOSH_RAGE23,
author = {Mancuso, Renato and Roozkhosh, Shahin and Hoornaert, Denis and Mun, Ju-Hyoung and Papon, Tarikul Islam and Athanassoulis, Manos},
title = {Software-Shaped Platforms},
year = {2023},
month = {May},
isbn = {9798400700491},
publisher = {Association for Computing Machinery},
address = {New York, NY, USA},
doi = {10.1145/3576914.3587546},
abstract = {This paper outlines the vision for a new type of software-shaped platforms, or SOSH platforms for short, that can be implemented in commercial CPU+FPGA platforms. At the core of the SOSH paradigm is the idea of exposing direct control over the flow of data exchanged between hardware components in embedded System-on-Chips (SoC). Data flow manipulation primitives are synthesized in reprogrammable hardware and interposed between central processors, memory modules, and I/O devices. A new layer of system software is then introduced to leverage such primitives and to achieve fine-grained control and introspection over the interaction of SoC resources. By turning memory and I/O data flows into manageable entities, a new degree of internal awareness can be achieved in complex systems. We first review recent works that are well aligned with the concept of data flow manipulation primitives that can be deployed in SOSH platforms. Next, we outline future research avenues concerning the use of the SOSH paradigm for workload profiling and prediction, to implement advanced memory models, and to perform security threat identification and mitigation.},
booktitle = {Proceedings of Cyber-Physical Systems and Internet of Things Week 2023},
pages = {185–191},
numpages = {7},
keywords = {predictability, software-shaped platforms, architectures},
location = {San Antonio, TX, USA},
series = {CPS-IoT Week `23}
type         = {conference},
durl         = {files/papers/SOSH_RAGE23.pdf}
}

@inproceedings{Cont_MCUs_RAGE23,
author = {Oliveira, Daniel and Chen, Weifan and Pinto, Sandro and Mancuso, Renato},
title = {Investigating and Mitigating Contention on Low-End Multi-Core Microcontrollers},
year = {2023},
month = {May},
isbn = {9798400700491},
publisher = {Association for Computing Machinery},
address = {New York, NY, USA},
doi = {10.1145/3576914.3587513},
booktitle = {Proceedings of Cyber-Physical Systems and Internet of Things Week 2023},
pages = {221–226},
numpages = {6},
location = {San Antonio, TX, USA},
series = {CPS-IoT Week `23}
type         = {conference},
durl         = {files/papers/Cont_MCUs_RAGE23.pdf}
}

@inproceedings{RelFab_ICDE23,
author = {Papon, Tarikul Islam and Mun, Ju-Hyoung and Roozkhosh, Shahin and Hoornaert, Denis and Sanaullah, Ahmed and Drepper, Ulrich and Mancuso, Renato and Athanassoulis, Manos},
title = {{Relational Fabric: Transparent Data Transformation}},
booktitle = {2023 IEEE International Conference on Data Engineering (ICDE)},
year = 2023,
month = {April},
address = {Anaheim, California, USA},
type = {conference},
durl = {files/papers/RelFab_ICDE23.pdf}
}

@inproceedings{MemPol23,
title        = {{MemPol: Policing Core Memory Bandwidth from Outside of the
Cores}},
author       = {Zuepke, Alexander and Bastoni, Andrea and Chen, Weifan and Caccamo, Marco and Mancuso, Renato},
year         = 2023,
month        = {May},
booktitle    = {
29th IEEE Real-Time and Embedded Technology and Applications Symposium
(RTAS 2023)
},
pages =      = {235-248},
doi          = {10.1109/RTAS58335.2023.00026},
address      = {San Antonio, Texas, USA},
type         = {conference},
durl         = {files/papers/MemPol_RTAS23.pdf},
}

@inproceedings{ExtTestingAvistar_AIAA23,
author = {Dantsker, Or D. and Caccamo, Marco and Mancuso, Renato},
title = {Expanded Flight & Ground Testing Data Set for an Unmanned Aircraft: Great Planes Avistar Elite},
booktitle = {AIAA SciTech 2023 Forum},
month = {Jan.},
address = {National Harbor, MD, USA},
year = {2023},
doi = {10.2514/6.2023-2105},
eprint = {https://arc.aiaa.org/doi/pdf/10.2514/6.2023-2105},
abstract = { View Video Presentation: https://doi.org/10.2514/6.2023-2105.vidThis paper presents the recently expanded flight and ground testing data set for a trainer-type unmanned aircraft, the Great Planes Avistar Elite. This is in the series of aircraft data sets that are being published online and freely available as part of the Unmanned Aerial Vehicle Database (UAVDB). The database is being continually expanded including aircraft and their components (e.g. propellers) as they are tested. This paper includes ground measurement, aircraft modeling, and flight testing results. Specifically, ground testing includes 3D scanning of geometry, moment of inertia testing, and propeller performance testing. Aircraft modeling includes a Solidworks CAD model, computational aerodynamics tool models in AVL, XFLR5, and Fluent, a propulsion system power model, and a flight simulation model in the X-Plane flight simulator. Flight testing results as well as testing and setup techniques are presented. Additionally, details regarding aircraft construction and instrumentation are provided. },
type = {conference},
durl = {files/papers/ExtTestingAvistar_AIAA23.pdf}
}

@inproceedings{RelMem,
author = {Roozkhosh, Shahin and Hoornaert, Denis and Mun, Ju-Hyoung and Papon, Tarikul Islam and Drepper, Ulrich and Mancuso, Renato and Athanassoulis, Manos},
title = {{Relational Memory: Native In-Memory Accesses on Rows
and Columns}},
booktitle = {2023 International Conference on Extending
Database Technology (EDBT)},
year = 2023,
address = {Ioannina, Greece},
doi = {10.48786/edbt.2023.06},
type = {conference},
durl =
{https://openproceedings.org/2023/conf/edbt/paper-177.pdf}
}

@inproceedings{RT_Bench_WiP_RTSS22,
author = {Nicolella, Mattia and Hoornaert, Denis and Roozkhosh, Shahin and Bastoni, Andrea and Mancuso, Renato},
title = {Know your Enemy: Benchmarking and Experimenting with Insight as a Goal},
booktitle = {WiP Session @ 43rd IEEE Real-Time Systems Symposium (RTSS@Work 2022)},
year = 2022,
address = {Houston, TX, USA},
type = {conference},
durl = {files/papers/RTBench_RTSS22.pdf}
}

@inproceedings{RT_DataReorg_WiP_RTSS22,
author = {Roozkhosh, Shahin and Hoornaert, Denis and Mancuso, Renato and Athanassoulis, Manos},
title = {{Hardware Data Re-organization Engine for Real-Time Systems}},
booktitle = {WiP Session @ 43rd IEEE Real-Time Systems Symposium (RTSS@Work 2022)},
year = 2022,
address = {Houston, TX, USA},
type = {conference},
durl = {files/papers/RT_RME_RTSS22.pdf}
}

@inproceedings{CAESAR_RTSS22,
author = {Roozkhosh, Shahin and Hoornaert, Denis and Mancuso, Renato},
title = {{CAESAR: Coherence-Aided Elective and Seamless
Alternative Routing via on-chip FPGA}},
booktitle = {43rd IEEE Real-Time Systems Symposium (RTSS
2022)},
year = 2022,
pages={356-369},
doi={10.1109/RTSS55097.2022.00038},
address = {Houston, TX, USA},
type = {conference},
durl = {files/papers/CAESAR_RTSS22.pdf}
}

@inbook{PropInstr_AIAA22,
author = {Dantsker, Or D. and Mancuso, Renato},
title = {Propulsion System Instrumentation Development and Integration
on Small- and Medium-Sized Electric Unmanned
Aircraft},
booktitle = {AIAA SCITECH 2022 Forum},
year = {2022},
doi = {10.2514/6.2022-2156},
eprint = {https://arc.aiaa.org/doi/pdf/10.2514/6.2022-2156},
abstract = { View Video Presentation:
https://doi.org/10.2514/6.2022-2156.vid - With the
increasing popularity of unmanned aircraft for both
research, military, and commercial applications,
significant effort has been undertaken in order to
improve these aircraft`s performance and flight
characteristics. Unmanned aircraft research and
development is often based on or culminates with
flight testing and significant effort has been
undertaken to integrate an increasing amount of
sensing into these vehicles. In the end all flight
testing efforts depend on the ability to acquire and
utilize high fidelity flight data from a large range
of sensors and devices. On electrically-propelled
unmanned aircraft, collecting propulsion system data
is especially vital in determining aircraft
state. Broadly, this includes: rotation rate(s) of
propellers, fans, or rotors; voltage, current, and
temperature at each system component, and energy
state of storage components. To collect these
measurements, sensors are placed throughout an
aircraft with data being sent to a central avionics
system, such as a data acquisition system or
autopilot. This paper focuses on the requirements,
design, development, and integration to perform
in-flight measurements of propulsion system
parameters on small- and medium-sized electric
unmanned aircraft. First, the paper provides an
overview for the development of a data acquisition
systems on unmanned aircraft followed by the
instrumentation aspects involved in integrating
propulsion system sensors and interfaces into
existing system architectures. Then, the paper
presents propulsion system sensing integration
examples in 3 different types of electric unmanned
aircraft used for research. }
type = {conference},
durl = {files/papers/PropSysInst_SciTech22.pdf}
}

@inproceedings{RTBench_RTNS22,
author = {Nicolella, Mattia and Roozkhosh, Shahin and Hoornaert, Denis
and Bastoni, Andrea and Mancuso, Renato},
title = {RT-Bench: An Extensible Benchmark Framework for the Analysis
and Management of Real-Time Applications},
year = {2022},
isbn = {9781450396509},
publisher = {Association for Computing Machinery},
address = {New York, NY, USA},
doi = {10.1145/3534879.3534888},
abstract = { Benchmarking is crucial for testing and validating any
system, including—and perhaps especially—real-time
systems. Typical real-time applications adhere to
well-understood abstractions: they exhibit a
periodic behavior, operate on a well-defined working
set, and strive for stable response time, avoiding
non-predicable factors such as page
faults. Unfortunately, available benchmark suites
fail to reflect key characteristics of real-time
applications. Practitioners and researchers must
resort to either benchmark heavily approximated
real-time environments or re-engineer available
benchmarks to add—if possible—the sought-after
features. Additionally, the measuring and logging
capabilities provided by most benchmark suites are
not tailored “out-of-the-box” to real-time
environments, and changing basic parameters such as
the scheduling policy often becomes a tiring and
error-prone exercise. In this paper, we present
RT-bench, an open-source framework adding standard
real-time features to virtually any existing
benchmark. Furthermore, RT-bench provides an
easy-to-use, unified command-line interface to
customize key aspects of the real-time execution of
a set of benchmarks. Our framework is guided by four
main criteria: 1) cohesive interface, 2) support for
periodic application behavior and deadline
semantics, 3) controllable memory footprint, and 4)
extensibility and portability. We have integrated
within the framework applications from the widely
used SD-VBS and IsolBench suites. We showcase a set
of use-cases that are representative of typical
real-time system evaluation scenarios, and that can
be easily conducted via RT-Bench.},
booktitle = {Proceedings of the 30th International Conference on
Real-Time Networks and Systems},
pages = {184–195},
numpages = {12},
keywords = {extensible, framework, periodic, portable, interference,
open-source, profiling, real-time, benchmark suite},
location = {Paris, France},
series = {RTNS 2022}
durl = {files/papers/RTBench_RTNS22.pdf}
type = {conference}
}

@inproceedings{SCHREG_OSPERT22,
place = {Country unknown/Code not available},
title = {On the Interplay of Computation and Memory Regulation in
Multicore Real-Time Systems},
year = {2022},
abstractNote = {The ever-increasing demand for high-performance in the
time-critical embedded domain has pushed the
adoption of powerful yet unpredictable heterogeneous
Systems-on-a-Chip. The shared memory subsystem,
which is known to be a major source of
unpredictability, has been extensively studied, and
many mitigation techniques have been proposed. Among
them, performance-counter-based regulation
techniques have seen widespread adoption. However,
the problem of combining performance-based
regulation with time-domain isolation has not
received enough attention. In this article, we
discuss our current work-in-progress on SHCReg
(Software Hardware Co-design Regulator). First, we
assess the limitations and benefits of combined CPU
and memory budgeting. Next, we outline a full-stack
hardware/software co-design architecture that aims
at improving the interplay between CPU and memory
isolation for mixed-criticality tasks running on the
same core.},
booktitle = {In Proceedings of the 16th Workshop on Operating Systems
Platforms for Embedded Real-Time Applications
(OSPERT 2022)},
author = {Hoornaert, Denis and Ghaemi, Golsana and Bastoni, Andrea and
Mancuso, Renato and Caccamo, Marco and Corradi,
Giulio},
durl = {files/papers/SCHREG_OSPERT22.pdf}
type = {conference}
}

@inproceedings{CloserLookRDT_RTNS22,
author = {Sohal, Parul and Bechtel, Michael and Mancuso, Renato and
Yun, Heechul and Krieger, Orran},
title = {A Closer Look at Intel Resource Director Technology (RDT)},
year = {2022},
isbn = {9781450396509},
publisher = {Association for Computing Machinery},
address = {New York, NY, USA},
doi = {10.1145/3534879.3534882},
abstract = { Unarbitrated contention over shared resources at
different levels of the memory hierarchy represents
a major source of temporal interference. Hardware
manufacturers are increasingly more receptive to
issues with temporal interference and are starting
to propose concrete solutions to mitigate the
problem. Intel Resource Director Technology (RDT)
represents one such attempt. Given the wide adoption
of Intel platforms, RDT features can be an
invaluable asset for the consolidation of real-time
systems on complex multi- and many-core
machines. Unfortunately, to date, a systematic
analysis of the capabilities introduced by the RDT
framework has not yet been conducted. Moreover, no
clear understanding has been matured about the
implementation-specific behavior of RDT primitives
across processor generations. And ultimately, the
ability of RDT to provide real-time guarantees is
yet to be established. In our work, we aim at
conducting a systematic investigation of the RDT
mechanisms from a real-time perspective. We
experimentally evaluate the functionality and
interpretability of RDT-aided allocation and
monitoring controls across the two most recent
processor generations. Our evaluations show that
while some features like Cache Allocation Technology
(CAT) yield promising results, the implementation of
other primitives such as Memory Bandwidth Allocation
(MBA) has much room for improvement. Moreover, in
some cases, the presented interfaces range from
blurry to incomplete, as is the case for MBA and
Memory Bandwidth Monitoring (MBM). },
booktitle = {Proceedings of the 30th International Conference on
Real-Time Networks and Systems},
pages = {127–139},
numpages = {13},
keywords = {shared cache partitioning, Resource Director Technology,
application profiling, bandwidth control, MBA,
performance guarantees, CMT, RDT, memory management,
MBM, CAT},
location = {Paris, France},
series = {RTNS 2022}
durl = {files/papers/CloserLookRDT_RTNS22.pdf}
type = {conference}
}

@inproceedings{virtio_rtss21,
title        = {
{A Real-Time virtio-based Framework for Predictable Inter-VM Communication}
},
author       = {
Schwaricke,  Gero and Tabish, Rohan and Pellizzoni, Rodolfo and Mancuso, Renato and Bastoni, Andrea and Zuepke, Alexander and Caccamo, Marco
},
year         = 2021,
month        = {Dec.},
booktitle    = {42nd IEEE Real-Time Systems Symposium (RTSS 2021)},
address      = {Dortmund, Germany},
type         = {conference},
pages={27-40},
doi={10.1109/RTSS52674.2021.00015},
durl         = {files/papers/Virtio_IVMC_RTSS21.pdf}
}

@inproceedings{AC_Compr_CoG21,
title = {Honey. I Shrunk The Actor: A Case Study on Preserving Performance with Smaller Actors in Actor-Critic RL},
author       = {Mysore, Siddharth and El Mabsout, Bassel and Mancuso, Renato and Saenko, Kate},
month        = {Aug.},
year = {2021},
publisher = {IEEE Press},
doi = {10.1109/CoG52621.2021.9619008},
abstract = {Actors and critics in actor-critic reinforcement learning algorithms are functionally separate, yet they often use the same network architectures. This case study explores the performance impact of network sizes when considering actor and critic architectures independently. By relaxing the assumption of architectural symmetry, it is often possible for smaller actors to achieve comparable policy performance to their symmetric counterparts. Our experiments show up to 99\% reduction in the number of network weights with an average reduction of 77 \% over multiple actor-critic algorithms on 9 independent tasks. Given that reducing actor complexity results in a direct reduction of run-time inference cost, we believe configurations of actors and critics are aspects of actor-critic design that deserve to be considered independently, particularly in resource-constrained applications or when deploying multiple actors simultaneously.},
booktitle = {IEEE Conference on Games (CoG)},
pages = {01–08},
numpages = {8},
address      = {Copenhagen, Denmark},
type         = {conference},
durl         = {files/papers/AsymmetricAC_CoG21.pdf}
}

@inproceedings{daq_solar_aiaa21,
title        = {
{Energy System Instrumentation and Data Acquisition for Flight Testing a
Long-Endurance, Solar-Powered Unmanned Aircraft}
},
author       = {Dantsker, Or D. and Caccamo, Marco and Mancuso, Renato},
year         = 2021,
month        = {July},
booktitle    = {AIAA Propulsion and Energy 2021 Forum},
address      = {Virtual Event},
doi          = {10.2514/6.2021-3721},
type         = {conference},
durl = {files/papers/EnerSysInst_AIAA21.pdf}
}

@inproceedings{SchIM_ECRTS21,
title        = {
{A Memory Scheduling Infrastructure for Multi-core Systems with
Re-programmable Logic}
},
author       = {Hoornaert, Denis and Roozkhosh, Shahin and Mancuso, Renato},
year         = 2021,
month        = {July},
booktitle    = {33rd Euromicro Conference on Real-Time Systems (ECRTS 2021)},
location     = {Dagstuhl, Germany},
publisher    = {Schloss Dagstuhl--Leibniz-Zentrum fuer Informatik},
address      = {Stuttgart, Germany},
series       = {Leibniz International Proceedings in Informatics (LIPIcs)},
editor       = {Bjorn B. Brandenburg},
pages =	{2:1--2:22},
ISBN =	{978-3-95977-192-4},
ISSN =	{1868-8969},
volume =	{196},
doi =		{10.4230/LIPIcs.ECRTS.2021.2},
type         = {conference},
durl         = {files/papers/SchIM_ECRTS21.pdf}
}

@inproceedings{BBProf_ECRTS21,
title        = {
{Governing with Insights: Towards Profile-driven Cache Management of
Black-Box Applications}
},
author       = {Ghaemi, Golsana and Tarapore, Dharmesh and Mancuso, Renato},
year         = 2021,
month        = {July},
booktitle    = {33rd Euromicro Conference on Real-Time Systems (ECRTS 2021)},
location     = {Dagstuhl, Germany},
publisher    = {Schloss Dagstuhl--Leibniz-Zentrum fuer Informatik},
address      = {Stuttgart, Germany},
series       = {Leibniz International Proceedings in Informatics (LIPIcs)},
editor       = {Bjorn B. Brandenburg},
pages =	{4:1--4:25},
ISBN =	{978-3-95977-192-4},
ISSN =	{1868-8969},
volume =	{196},
doi =		{10.4230/LIPIcs.ECRTS.2021.4},
type         = {conference},
durl         = {files/papers/BBProf_ECRTS21.pdf}
}

@inproceedings{brainfreeze_RTAS_wip_21,
title        = {{Identifying Unexpected Inter-core Interference Induced by Shared Cache}},
author       = {Hoornaert, Denis and Roozkhosh, Shahin and Mancuso, Renato and Caccamo, Marco},
year         = 2021,
month        = {May},
booktitle    = {
WiP Session @ 27th IEEE Real-Time and Embedded Technology and Applications
Symposium (RTAS 2021)
},
address      = {Online},
type         = {conference},
durl         = {files/papers/CPU_Brainfreeze_RTAS21_WiP.pdf}
}

@inproceedings{regul_RL_ICRA21,
title        = {
{Regularizing Action Policies for Smooth Control with Reinforcement
Learning}
},
author       = {Mysore, Siddharth and El Mabsout, Bassel and Mancuso, Renato and Saenko, Kate},
year         = 2021,
month        = {May},
booktitle    = {IEEE International Conference on Robotics and Automation (ICRA`21)},
address      = {Xi`an, China},
type         = {conference},
durl         = {files/papers/ICRA21_1616_FI.pdf},
doi          = {10.1109/ICRA48506.2021.9561138},
slides       = {https://youtu.be/yFjkiuXvNrU}
}

@inproceedings{ewarp20,
title        = {
{E-WarP: a System-wide Framework for Memory Bandwidth Profiling and
Management}
},
author       = {Sohal, Parul and Tabish, Rohan and Drepper, Ulrich and Mancuso, Renato},
year         = 2020,
month        = {Dec.},
booktitle    = {41st IEEE Real-Time Systems Symposium (RTSS 2020)},
address      = {Houston, TX, USA},
pages        = {345--357},
doi          = {10.1109/RTSS49844.2020.00039},
type         = {conference}
}
,
remark = {Best Student Paper Award},
durl = {files/papers/EWarP_RTSS20_final.pdf},
}

@inproceedings{tabish2020commm,
title        = {
{SCE-Comm: A Real-Time Inter-Core Communication Framework for Strictly
Partitioned Multi-core Processors}
},
author       = {
Tabish, Rohan and Wen, Jen-Yang and Pellizzoni, Rodolfo and Mancuso, Renato and Yun, Heechul and Caccamo, Marco and Sha, Lui
},
year         = 2020,
month        = {June},
booktitle    = {9th Mediterranean Conference on Embedded Computing (MECO 2020)},
address      = {Budva, Montenegro},
pages        = {1--6},
doi          = {10.1109/MECO49872.2020.9134178},
type         = {conference},
durl         = {files/papers/SCE_Comm_MECO20.pdf}
}

@inproceedings{bansal2020cache,
title        = {{Reconciling Predictability and Coherent Caching}},
author       = {
Bansal, Ayoosh and Singh, Jayati and Hao, Yifan and Wen, Jen-Yang and Mancuso, Renato and Caccamo, Marco
},
year         = 2020,
month        = {June},
booktitle    = {9th Mediterranean Conference on Embedded Computing (MECO 2020)},
address      = {Budva, Montenegro},
pages        = {1--6},
doi          = {10.1109/MECO49872.2020.9134262},
type         = {conference},
durl         = {files/papers/MECO_2020_Cache_Coherence.pdf}
}

@inproceedings{PLIM20,
title        = {{The Potential of Programmable Logic in the Middle: Cache Bleaching}},
author       = {Roozkhosh, Shahin and Mancuso, Renato},
year         = 2020,
month        = {April},
booktitle    = {
26th IEEE Real-Time and Embedded Technology and Applications Symposium
(RTAS 2020)
},
address      = {Sydney, Australia},
doi          = {10.1109/RTAS48715.2020.00006},
type         = {conference},
remark       = {Best Paper Award},
durl         = {files/papers/PLIM_rtas20.pdf},
slides       = {files/slides/PLIM_RTAS20}
}

@inproceedings{Continued_Solar_AIAAScitech20,
title        = {
{Continued Development and Flight Testing of a Long-Endurance Solar-Powered
Unmanned Aircraft: UIUC-TUM Solar Flyer}
},
author       = {Dantsker, Or D. and Theile, Mirco and Caccamo, Marco and Yu, Simon and Vahora, Moiz and Mancuso, Renato},
year         = 2020,
month        = {Jan.},
booktitle    = {AIAA Scitech 2020 Forum},
address      = {Orlando, FL, USA},
doi          = {10.2514/6.2020-0781},
type         = {conference},
durl         = {files/papers/Continued_Solar_AIAAScitech20.pdf}
}

@inproceedings{UAVDB_Avistar_AIAAScitech20,
title        = {
{Flight & Ground Testing Data Set for an Unmanned Aircraft: Great Planes
Avistar Elite}
},
author       = {Dantsker, Or D. and Caccamo, Marco and Vahora, Moiz and Mancuso, Renato},
year         = 2020,
month        = {Jan.},
booktitle    = {AIAA Scitech 2020 Forum},
address      = {Orlando, FL, USA},
doi          = {10.2514/6.2020-0780},
type         = {conference},
durl         = {files/papers/UAVDB_Avistar_AIAAScitech20.pdf}
}

@inproceedings{DMLRU_ECRTS19,
title        = {{Impact of DM-LRU on WCET: a Static Analysis Approach}},
author       = {Mancuso, Renato and Yun, Heechul and Puaut, Isabelle},
year         = 2019,
month        = {July},
booktitle    = {31th Euromicro Conference on Real-Time Systems (ECRTS 2019)},
location     = {Dagstuhl, Germany},
publisher    = {Schloss Dagstuhl--Leibniz-Zentrum fuer Informatik},
address      = {Stuttgart, Germany},
series       = {Leibniz International Proceedings in Informatics (LIPIcs)},
volume       = 107,
pages        = {17:1--17:25},
doi          = {10.4230/LIPIcs.ECRTS.2019.17},
editor       = {Sophie Quinton},
type         = {conference},
durl         = {files/papers/DM-LRU_ECRTS19.pdf},
slides       = {files/slides/DM_LRU}
}

@inproceedings{mixcrit_mpsoc_ECRTS19,
title        = {
{Designing Mixed Criticality Applications on Modern Heterogeneous MPSoC
Platforms}
},
author       = {
Gracioli, Giovani and Tabish, Rohan and Mancuso, Renato and Mirosanlou, Reza and Pellizzoni, Rodolfo and Caccamo, Marco
},
year         = 2019,
month        = {July},
booktitle    = {31th Euromicro Conference on Real-Time Systems (ECRTS 2019)},
location     = {Dagstuhl, Germany},
publisher    = {Schloss Dagstuhl--Leibniz-Zentrum fuer Informatik},
address      = {Stuttgart, Germany},
series       = {Leibniz International Proceedings in Informatics (LIPIcs)},
volume       = 107,
pages        = {27:1--27:25},
doi          = {10.4230/LIPIcs.ECRTS.2019.27},
editor       = {Sophie Quinton},
remark       = {Outstanding Paper Award},
type         = {conference},
durl         = {files/papers/MixCrit_MPSOC_ECRTS19.pdf}
}

@inproceedings{MARSNet_AIAA19,
title        = {
{Design of Multi-Agent UAV Simulator to Support the Development of the
MARSNet Communication Protocol}
},
author       = {Ponniah, Jonathan and Dantsker, Or D. and Mancuso, Renato},
year         = 2019,
month        = {June},
booktitle    = {AIAA Aviation 2019 Forum},
address      = {Dallas, TX, USA},
doi          = {10.2514/6.2019-3114},
durl = {files/papers/MARSNet_AIAA19.pdf},
type         = {conference}
}

@inproceedings{FlightTest_AIAAScitech19,
title        = {
{Flight Testing Data Set for Subscale GA Aircraft: 26\%-scale Cub Crafters
CC11-100 Sport Cub S2}
},
author       = {Dantsker, Or D. and Mancuso, Renato},
year         = 2019,
month        = {Jan.},
booktitle    = {AIAA Scitech 2019 Forum},
address      = {San Diego, CA, USA},
doi          = {10.2514/6.2019-1616},
type         = {conference},
durl         = {files/papers/FlightTest_AIAAScitech19.pdf}
}

@inproceedings{UKL_hotos19,
title        = {{Unikernels: The Next Stage of Linux`s Dominance}},
author       = {Raza, Ali and Sohal, Parul and Cadden, James and Appavoo, Jonathan and Drepper, Ulrich and Jones, Richard and Krieger, Orran and Mancuso, Renato and Woodman, Larry},
year         = 2019,
month        = {May},
booktitle    = {17th Workshop on Hot Topics in Operating Systems (HotOS 2019)},
address      = {Bertinoro, Italy},
pages        = {7--13},
doi          = {10.1145/3317550.3321445},
type         = {conference},
durl         = {files/papers/UKL_hotos19.pdf}
}

@inproceedings{FDAQ_AIAAScitech19,
title        = {
{Flight Data Acquisition Platform Development, Integration, and Operation
on Small-to Medium-Sized Unmanned Aircraft}
},
author       = {Dantsker, Or D. and Mancuso, Renato},
year         = 2019,
month        = {Jan.},
booktitle    = {AIAA Scitech 2019 Forum},
address      = {San Diego, CA, USA},
doi          = {10.2514/6.2019-1262},
type         = {conference},
durl         = {files/papers/FDAQ_AIAAScitech19.pdf}
}

@inproceedings{virtIDArtas19,
title        = {
{Deterministic Memory Hierarchy and Virtualization for Modern Multi-Core
Embedded Systems}
},
author       = {Kloda, Tomasz and Solieri, Marco and Mancuso, Renato and Capodieci, Nicola and Valente, Paolo and Bertogna, Marko},
year         = 2019,
month        = {April},
booktitle    = {
25th IEEE Real-Time and Embedded Technology and Applications Symposium
(RTAS 2019)
},
address      = {Montreal, Canada},
pages        = {1--14},
doi          = {10.1109/RTAS.2019.00009},
type         = {conference},
durl         = {files/papers/virt_IDA_rtas19.pdf}
}

@inproceedings{dantsker2018design,
title        = {
{Design, Development, and Initial Testing of a Computationally-Intensive,
Long-Endurance Solar-Powered Unmanned Aircraft}
},
author       = {Dantsker, Or D. and Theile, Mirco and Caccamo, Marco and Mancuso, Renato},
year         = 2018,
month        = {June},
booktitle    = {36th Applied Aerodynamics Conference},
address      = {Atlanta, GA, USA},
doi          = {https://doi.org/10.2514/6.2018-4217},
type         = {conference},
durl         = {files/papers/solar_UAV_APA18.pdf}
}

@inproceedings{dyn_bw_rtss18,
title        = {
{Analysis of Dynamic Memory Bandwidth Regulation in Multi-core Real-Time
Systems}
},
author       = {Agrawal, Ankit and Mancuso, Renato and Pellizzoni, Rodolfo and Fohler, Gerhard},
year         = 2018,
month        = {Dec.},
booktitle    = {39th IEEE Real-Time Systems Symposium (RTSS 2018)},
address      = {Nashville, TN, USA},
pages        = {230--241},
doi          = {10.1109/RTSS.2018.00040},
type         = {conference},
durl         = {files/papers/dynbw_wcet_rtss18.pdf}
}

@inproceedings{mpsoc_mem_ospert18,
title        = {{Evaluating the Memory Subsystem of Configurable Heterogeneous MPSoC}},
author       = {
Bansal, Ayoosh and Tabish, Rohan and Gracioli, Giovani and Mancuso, Renato and Pellizzoni, Rodolfo and Caccamo, Marco},
year         = 2018,
year         = 2018,
month        = {July},
booktitle    = {
14th Annual Workshop on Operating Systems Platforms for Embedded Real-Time
Applications (OSPERT 2018)
},
address      = {Barcelona, Spain},
pages        = {55--60},
type         = {conference},
durl         = {files/papers/mpsoc_mem_OSPERT18.pdf}
}

@inproceedings{cl_verif_ospert18,
title        = {{Verification of OS-level Cache Management}},
author       = {Mancuso, Renato and Chaki, Sagar},
year         = 2018,
month        = {July},
booktitle    = {
14th Annual Workshop on Operating Systems Platforms for Embedded Real-Time
Applications (OSPERT 2018)
},
address      = {Barcelona, Spain},
pages        = {37--42},
type         = {conference},
durl         = {files/papers/cl_verif_OSPERT18.pdf},
slides       = {files/slides/Verif_OSPERT18}
}

@inproceedings{farshchideterministic,
title        = {
{Deterministic Memory Abstraction and Supporting Multicore System
Architecture}
},
author       = {
Farshchi, Farzad and Valsan, Prathap Kumar and Mancuso, Renat and Yun, Heechul
},
year         = 2018,
month        = {July},
booktitle    = {30th Euromicro Conference on Real-Time Systems (ECRTS 2018)},
location     = {Dagstuhl, Germany},
publisher    = {Schloss Dagstuhl--Leibniz-Zentrum fuer Informatik},
address      = {Barcelona, Spain},
series       = {Leibniz International Proceedings in Informatics (LIPIcs)},
volume       = 106,
pages        = {1:1--1:25},
doi          = {10.4230/LIPIcs.ECRTS.2018.1},
isbn         = {978-3-95977-075-0},
issn         = {1868-8969},
editor       = {Sebastian Altmeyer},
urn          = {urn:nbn:de:0030-drops-90010},
type         = {conference},
durl         = {
http://drops.dagstuhl.de/opus/volltexte/2018/9001/pdf/LIPIcs-ECRTS-2018-1.pdf
}
}

@inproceedings{mancuso_et_al:LIPIcs:2017:7168,
title        = {
{WCET Derivation under Single Core Equivalence with Explicit Memory Budget
Assignment}
},
author       = {Mancuso, Renato and Pellizzoni, Rodolfo and Tokcan, Neriman and Caccamo, Marco},
year         = 2017,
month        = {July},
booktitle    = {29th Euromicro Conference on Real-Time Systems (ECRTS 2017)},
location     = {Dagstuhl, Germany},
publisher    = {Schloss Dagstuhl--Leibniz-Zentrum fuer Informatik},
address      = {Dubrovnik, Croatia},
series       = {Leibniz International Proceedings in Informatics (LIPIcs)},
volume       = 76,
pages        = {3:1--3:23},
doi          = {10.4230/LIPIcs.ECRTS.2017.3},
isbn         = {978-3-95977-037-8},
issn         = {1868-8969},
editor       = {Marko Bertogna},
urn          = {urn:nbn:de:0030-drops-71684},
durl         = {
http://drops.dagstuhl.de/opus/volltexte/2017/7168/pdf/LIPIcs-ECRTS-2017-3.pdf
},
annote       = {
Keywords: real-time multicore, WCET, single-core equivalence, DRAM
management, certification
},
type         = {conference},
slides       = {files/slides/ECRTS17_UnevenBW/}
}

@inproceedings{dantsker2017rolling,
title        = {{A Rolling Rig for Propeller Performance Testing}},
author       = {Dantsker, Or D. and Selig, Michael S. and Mancuso, Renato},
year         = 2017,
month        = {June},
booktitle    = {35th AIAA Applied Aerodynamics Conference},
address      = {Denver, CO, USA},
doi          = {10.2514/6.2017-3745},
type         = {conference},
durl         = {files/papers/rolling_rig_aiaa17.pdf}
}

@inproceedings{8046320,
title        = {{Restart-based fault-tolerance: System design and schedulability analysis}},
author       = {Abdi, Fardin A. T. and Mancuso, Renato and Tabish, Rohan and Caccamo, Marco},
year         = 2017,
month        = {Aug},
booktitle    = {
23rd IEEE International Conference on Embedded and Real-Time Computing
Systems and Applications (RTCSA 2017)
},
address      = {Hsinchu, Taiwan},
volume       = {},
number       = {},
pages        = {1--10},
doi          = {10.1109/RTCSA.2017.8046320},
issn         = {},
type         = {conference},
abstract     = {
Embedded systems in safety-critical environments are continuously required
to deliver more performance and functionality, while expected to provide
verified safety guarantees. Nonetheless, platform-wide software
verification (required for safety) is often expensive. Therefore, design
methods that enable utilization of components such as real-time operating
systems (RTOS), without requiring their correctness to guarantee safety, is
necessary. In this paper, we propose a design approach to deploy
safe-by-design embedded systems. To attain this goal, we rely on a small
core of verified software to handle faults in applications and RTOS and
recover from them while ensuring that timing constraints of safety-critical
tasks are always satisfied. Faults are detected by monitoring the
application timing and fault-recovery is achieved via full platform restart
and software reload, enabled by the short restart time of embedded systems.
Schedulability analysis is used to ensure that the timing constraints of
critical plant control tasks are always satisfied in spite of faults and
consequent restarts. We derive schedulability results for four
restart-tolerant task models. We use a simulator to evaluate and compare
the performance of the considered scheduling models.
},
keywords     = {
embedded systems;operating systems (computers);safety-critical
software;scheduling;software fault tolerance;software performance
evaluation;RTOS;application timing monitoring;critical plant control
tasks;embedded systems;fault-recovery monitoring;full platform
restart;real-time operating systems;restart-based
fault-tolerance;restart-tolerant task models;safe-by-design embedded
systems;safety-critical environments;schedulability analysis;software
reload;system design;timing
constraints;Actuators;Ellipsoids;Safety;Software;Switches;Timing
},
durl         = {https://arxiv.org/pdf/1705.02412.pdf},
slides       = {files/slides/RTCSA17_ResetRec/}
}

@inproceedings{8046314,
title        = {
{A scheduling framework for handling integrated modular avionic systems on
multicore platforms}
},
author       = {Melani, Alessandra and Mancuso, Renato and Caccamo, Marco and Buttazzo, Giorgio and Freitag, Johannes and Uhrig, Sascha},
year         = 2017,
month        = {Aug},
booktitle    = {
23rd IEEE International Conference on Embedded and Real-Time Computing
Systems and Applications (RTCSA 2017)
},
address      = {Hsinchu, Taiwan},
volume       = {},
number       = {},
pages        = {1--10},
doi          = {10.1109/RTCSA.2017.8046314},
issn         = {},
type         = {conference},
abstract     = {
Although multicore chips are quickly replacing uniprocessor ones,
safety-critical embedded systems are still developed using single processor
architecture. The reasons mainly concern predictability and certification
issues. This paper proposes a scheduling framework for handling Integrated
Modular Avionics (IMA) on multicore platforms providing predictability as
well as flexibility in managing dynamic load conditions and unexpected
temporal misbehaviors of multicore. A new computational model is proposed
to allow specifying a higher degree of flexibility and minimum performance
requirements. Schedulability analysis is derived for providing off-line
guarantees of real-time constraints in worst-case scenarios, and an
efficient reclaiming mechanism is proposed to improve the average-case
performance. Simulation and experimental results are reported to validate
the proposed approach.
},
keywords     = {
avionics;multiprocessing systems;processor scheduling;IMA;dynamic load
conditions management;integrated modular avionic systems;integrated modular
avionics;multicore platforms;multicore unexpected temporal
misbehaviors;off-line guarantees;real-time constraints;reclaiming
mechanism;schedulability analysis;scheduling framework;worst-case
scenarios;Aerospace electronics;Interference;Multicore processing;Real-time
systems;Servers;Switches
},
durl         = {files/papers/mc_ima_RTCSA17.pdf},
slides       = {files/slides/RTCSA17_MC_IMA/}
}

@inproceedings{7939055,
title        = {
{A Reliable and Predictable Scratchpad-centric OS for Multi-core Embedded
Systems}
},
author       = {Tabish, Rohan and Mancuso, Renato and Wasly, Saud and Phatak, Sujit S. and Pellizzoni, Rodolfo and Caccamo, Marco},
year         = 2017,
month        = {April},
booktitle    = {
23rd IEEE Real-Time and Embedded Technology and Applications Symposium
(RTAS 2017)
},
address      = {Pittsburgh, PA, USA},
volume       = {},
number       = {},
pages        = {377--388},
doi          = {10.1109/RTAS.2017.1},
issn         = {},
type         = {conference},
abstract     = {
The reliable use of multi-core platforms for designing safety-critical
systems still represents an open challenge. Recently, the FAA [1] has
formally expressed its concern towards the use of multi-core systems in
avionics. The sharing of hardware resources introduces non-trivial timing
dependencies between logically independent components (e.g. cores);
additionally, the increase in size of circuitry, memory resources, and
transistor density makes these platforms more susceptible to transient
memory (soft) errors. This work addresses the problem of memory soft errors
and their recovery at an OS/platform level on commercial multi-core
systems. Proposed strategy considers the schedulability impact of recovery
procedures on hard real-time workloads. Finally, the implementation of a
SPM-centric OS with the proposed OS-level strategies was performed by using
a commercially available multi-core platform. The design has been validated
and evaluated using a combination of synthetic and realistic (EEMBC)
benchmarks.
},
keywords     = {
avionics;embedded systems;multiprocessing systems;operating systems
(computers);safety-critical software;scheduling;avionics;multicore embedded
systems;safety-critical systems;schedulability;scratchpad centric OS;Error
correction codes;Hardware;Multicore processing;Random access
memory;Real-time systems;Reliability;Timing
},
durl         = {files/papers/spm_os_rec_RTAS17.pdf}
}

@inproceedings{7459468,
title        = {{Speed optimization for tasks with two resources}},
author       = {Melani, Alessandra and Mancuso, Renato and Cullina, Daniel and Caccamo, Marco and Thiele, Lothar},
year         = 2016,
month        = {March},
booktitle    = {19th Design, Automation Test in Europe Conference Exhibition (DATE 2016)},
location     = {San Jose, CA, USA},
publisher    = {EDA Consortium},
address      = {Dresden, Germany},
volume       = {},
number       = {},
pages        = {1072--1077},
doi          = {10.3850/9783981537079_0404},
issn         = {},
editor       = {Jürgen Teich},
type         = {conference},
abstract     = {
Multiple resource co-scheduling algorithms and pipelined execution models
are becoming increasingly popular, as they better capture the heterogeneous
nature of modern architectures. The problem of scheduling tasks composed of
multiple stages tied to different resources goes under the name of
“flow-shop scheduling”. This problem, studied since the `50s to optimize
production plants, is known to be NP-hard in the general case. In this
paper, we consider a specific instance of the flow-shop task model that
captures the behavior of a two-resource (DMA-CPU) system. In this setting,
we study the problem of selecting the optimal operating speed of either
resource with the goal of minimizing power consumption while meeting
schedulability constraints. We derive an algorithm that finds an exact
solution to the problem in polynomial time, hence it is suitable for online
operation even in the presence of variable real-time workload.
},
keywords     = {
computational complexity;flow shop scheduling;optimisation;resource
allocation;DMA-CPU system;NP-hard problem;flow-shop scheduling;pipelined
execution model;polynomial time;resource coscheduling algorithm;speed
optimization;task scheduling;Clocks;Computer architecture;Job shop
scheduling;Load modeling;Optimal scheduling;Real-time systems
},
durl         = {files/papers/flowshow_date16.pdf}
}

@inproceedings{7733561,
title        = {
{Reset-based recovery for real-time cyber-physical systems with temporal
safety constraints}
},
author       = {Abad, Fardin A. T. and Mancuso, Renato and Bak, Stanley and Dantsker, Or D. and Caccamo, Marco},
year         = 2016,
month        = {Sept},
booktitle    = {
21st IEEE International Conference on Emerging Technologies and Factory
Automation (ETFA 2016)
},
address      = {Berlin, Germany},
volume       = {},
number       = {},
pages        = {1--8},
doi          = {10.1109/ETFA.2016.7733561},
issn         = {},
type         = {conference},
abstract     = {
In traditional computing systems, software problems are often resolved by
platform restarts. This approach, however, cannot be naïvely used in
cyber-physical systems (CPS). In fact, in this class of systems, ensuring
safety strictly depends on the ability to respect hard real-time
constraints. Several adaptations of the Simplex architecture have been
proposed to guarantee safety in spite of misbehaving software components.
However, the problem of performing recovery into a fully operational state
has not been extensively addressed. In this work, we discuss how resets can
be used in CPS as an effective strategy to recover from a variety of
software faults. Our work extends the Simplex architecture in a number of
directions. First, we provide sufficient conditions under which safety is
guaranteed in spite of fault-induced resets. Second, we introduce a novel
technique to express not only state-dependent safety constraints, as
typically done in Simplex, but also time-dependent safety properties.
Finally, through a proof-of-concept minimal implementation on a small R/C
helicopter and simulation-based system modeling, we show the effectiveness
of the proposed recovery strategy under the assumed fault model.
},
keywords     = {
cyber-physical systems;object-oriented programming;security of data;CPS;R/C
helicopter;Simplex architecture;computing systems;fault model;fault-induced
resets;real-time constraints;real-time cyber-physical systems;reset-based
recovery;simulation-based system modeling;software components;software
faults;software problems;state-dependent safety constraints;temporal safety
constraints;time-dependent safety properties;Computer architecture;Control
systems;Ellipsoids;Helicopters;Real-time systems;Safety;Software
},
durl         = {files/papers/reset_based_ETFA16.pdf}
}

@inproceedings{7461321,
title        = {{A Real-Time Scratchpad-Centric OS for Multi-Core Embedded Systems}},
author       = {
Tabish, Rohan and Mancuso, Renato and Wasly, Saud and Alhammad, Ahmed and Phatak, Sujit S. and Pellizzoni, Rodolfo and Caccamo, Marco},
year         = 2016,
month        = {April},
booktitle    = {
22nd IEEE Real-Time and Embedded Technology and Applications Symposium
(RTAS 2016)
},
address      = {Vienna, Austria},
volume       = {},
number       = {},
pages        = {1--11},
doi          = {10.1109/RTAS.2016.7461321},
issn         = {},
type         = {conference},
abstract     = {
Multi-core processors have replaced single-core systems in almost every
segment of the industry. Unfortunately, their increased complexity often
causes a loss of temporal predictability which represents a key requirement
for hard real-time systems. Major sources of unpredictability are the
shared low level resources, such as the memory hierarchy and the I/O
subsystem. In this paper, we approach the problem of shared resource
arbitration at an OS-level and propose a novel scratchpad-centric OS design
for multi-core platforms. In the proposed OS, the predictable usage of
shared resources across multiple cores represents a central design-time
goal. Hence, we show (i) how contention-free execution of real-time tasks
can be achieved on scratchpad-based architectures, and (ii) how a
separation of application logic and I/O perations in the time domain can be
enforced. To validate the proposed design, we implemented the proposed OS
using a commercial-off-the-shelf (COTS) platform. Experiments show that
this novel design delivers predictable temporal behavior to hard real-time
tasks, and it improves performance up to 2.1× compared to traditional
approaches.
},
keywords     = {
embedded systems;multiprocessing systems;operating systems (computers);COTS
platform;I/O subsystem;application logic
separation;commercial-off-the-shelf platform;memory hierarchy;multicore
embedded systems;multicore processors;real-time scratchpad-centric
OS;scratchpad-based architectures;shared resource arbitration;single-core
systems;time domain;Aerospace electronics;Engines;Hardware;Multicore
processing;Operating systems;Real-time systems
},
remark       = {Best Presentation Award},
durl         = {files/papers/spm_os_RTAS16.pdf},
slides       = {files/slides/RTAS2016_SPM_OS/}
}

@inproceedings{gao2015exploiting,
title        = {
{Exploiting structured human interactions to enhance estimation accuracy in
cyber-physical systems}
},
author       = {
Gao, Yunlong and Hu, Shaohan and Mancuso, Renato and Wang, Hongwei and Kim,
Minje and Wu, PoLiang and Su, Lu and Sha, Lui and Abdelzaher, Tarek
},
year         = 2015,
month        = {April},
booktitle    = {
6th ACM/IEEE International Conference on Cyber-Physical Systems (ICCPS
2015)
},
address      = {Seattle, WA, USA},
pages        = {60--69},
doi          = {10.1145/2735960.2735965},
organization = {ACM},
type         = {conference},
durl         = {files/papers/struct_int_iccps15.pdf}
}

@incollection{dantsker2015sdac,
title        = {
{SDAC-UAS: A Sensor Data Acquisition Unmanned Aerial System for Flight
State Monitoring and Aerodynamic Data Collection}
},
author       = {
Dantsker, Or D. and Louis, Andrew V and Mancuso, Renato and Caccamo, Marco
and Selig, Michael S.
},
year         = 2015,
month        = {Jan.},
booktitle    = {10th AIAA Infotech @ Aerospace},
address      = {Kissimmee, FL, USA},
doi          = {10.2514/6.2015-0987},
type         = {conference},
durl         = {files/papers/sdaq_uas_aiaa15.pdf}
}

@inproceedings{7318281,
title        = {{Using traffic phase shifting to improve AFDX link utilization}},
author       = {Mancuso, Renato and Louis, Andrew V. and Caccamo, Marco},
year         = 2015,
month        = {Oct},
booktitle    = {
15th ACM SIGBED International Conference on Embedded Software (EMSOFT 2015)
},
address      = {Amsterdam, The Netherlands},
volume       = {},
number       = {},
pages        = {256--265},
doi          = {10.1109/EMSOFT.2015.7318281},
issn         = {},
type         = {conference},
abstract     = {
The Avionic Full-Duplex Switched Ethernet (AFDX) is a data network
certified for avionic operations. AFDX closely follows the IEEE 802.3
(Ethernet) standard for packet forwarding. On top of that, bandwidth
enforcement using traffic shaping is performed to provide deterministic
delivery guarantees. The design of an AFDX network, however, imposes that
bandwidth enforcement is performed at a coarse granularity. This, together
with the tight requirements on transmission jitter, determines a low
utilization of the physical links. In this work, we propose traffic phase
shifting (TPS) as a way to increase the granularity of bandwidth assignment
to nodes of an AFDX network using logic time synchronization among traffic
sources. Specifically, we leverage the periodic nature of real-time traffic
and use phase-shifing to prevent link congestion. This in turns allows a
more fine-grained bandwidth control via the AFDX protocol. We show that TPS
leads to significant improvements in terms of per-link utilization without
violating predictability.
},
keywords     = {
avionics;local area networks;protocols;real-time systems;telecommunication
traffic;AFDX protocol;IEEE 802.3 standard;TPS;avionic full-duplex switched
Ethernet;bandwidth assignment;bandwidth enforcement;coarse
granularity;deterministic delivery guarantees;fine-grained bandwidth
control;link utilization improvement;logic time synchronization;packet
forwarding;physical links;real-time traffic;traffic phase shifting;traffic
shaping;transmission jitter;Aerospace
electronics;Aggregates;Bandwidth;Jitter;Mathematical model;Noise
measurement;Standards
},
durl         = {files/papers/afdx_emsoft15.pdf},
slides       = {files/slides/AFDX_emsoft/}
}

@inproceedings{7299854,
title        = {
{A Memory Access Detection Methodology for Accurate Workload
Characterization}
},
author       = {Cesati, Marco and Mancuso, Renato and Betti, Emiliano and Caccamo, Marco},
year         = 2015,
month        = {Aug},
booktitle    = {
21st IEEE International Conference on Embedded and Real-Time Computing
Systems and Applications (RTCSA 2015)
},
address      = {Hong Kong, China},
volume       = {},
number       = {},
pages        = {141--148},
doi          = {10.1109/RTCSA.2015.30},
issn         = {2325-1271},
type         = {conference},
abstract     = {
Tools for memory access detection are widely used, playing an important
role especially in real-time systems. For example, on multi-core platforms,
the problem of co-scheduling CPU and memory resources with hard real-time
constraints requires a deep understanding of the memory access patterns of
the deployed task set. While code execution flow can be analyzed by
considering the control-flow graph and reasoning in terms of basic blocks,
a similar approach cannot apply to data accesses. In this paper, we propose
MadT, a tool that uses a novel mechanism to perform memory access detection
of general purpose applications. MadT does not perform binary
instrumentation and always executes application code natively on the
platform. Hence it can operate entirely in user-space without sand-boxing
the task under analysis. Furthermore, MadT provides detailed symbolic
information about the accessed memory structures, so it is able to
translate the virtual addresses to their original symbolic variable names.
Finally, it requires no modifications to application source code. The
proposed methodology relies on existing OS-level capabilities. In this
paper, we describe how MadT has been implemented on commercial hardware and
compare its performance with state-of-the-art software techniques for
memory access detection.
},
keywords     = {
multiprocessing systems;real-time systems;storage allocation;CPU resource
co-scheduling;MadT tool;application source code;code execution flow
analysis;control-flow graph;hard-real-time constraints;memory access
detection methodology;memory access patterns;memory resource
co-scheduling;memory structures;multicore platforms;real-time
systems;symbolic information;symbolic variable names;virtual
addresses;workload characterization;Dynamic
scheduling;Hardware;Instruments;Libraries;Memory
management;Permission;Resource management
},
durl         = {files/papers/madt_rtcsa15.pdf},
slides       = {files/slides/MadT_rtcsa15/}
}

@inproceedings{7176036,
title        = {{WCET(m) Estimation in Multi-core Systems Using Single Core Equivalence}},
author       = {Mancuso, Renato and Pellizzoni, Rodolfo and Caccamo, Marco and Sha, Lui and Yun, Heechul},
year         = 2015,
month        = {July},
booktitle    = {27th Euromicro Conference on Real-Time Systems (ECRTS 2015)},
address      = {Lund, Sweden},
volume       = {},
number       = {},
pages        = {174--183},
doi          = {10.1109/ECRTS.2015.23},
issn         = {1068-3070},
type         = {conference},
abstract     = {
Multi-core platforms represent the answer of the industry to the increasing
demand for computational capabilities. From a real-time perspective,
however, the inherent sharing of resources, such as memory subsystem and
I/O channels, creates inter-core timing interference among critical tasks
and applications deployed on different cores. As a result, modular per-core
certification cannot be performed, meaning that: (1) current industrial
engineering processes cannot be reused, (2) software developed and
certified for single-core chips cannot be deployed on multi-core platforms
as is. In this work, we propose the Single Core Equivalence (SCE)
technology: a framework of OS-level techniques designed for commercial
(COTS) architectures that exports a set of equivalent single-core virtual
machines from a multi-core platform. This allows per-core schedulability
results to be calculated in isolation and to hold when multiple cores of
the system run in parallel. Thus, SCE allows each core of a multi-core chip
to be considered as a conventional single-core chip, ultimately enabling
industry to reuse existing software, schedulability analysis methodologies
and engineering processes.
},
keywords     = {
resource allocation;shared memory systems;software reusability;IO
channels;OS-level techniques;WCET estimation;commercial
architectures;computational capabilities;existing software reuse;industrial
engineering processes;inter-core timing interference;memory
subsystem;multi-core systems using single core equivalence;multicore
platforms;resource sharing;schedulability analysis methodologies;single
core equivalence technology;single-core chips;software engineering
processes;Bandwidth;Delays;Hardware;Multicore processing;Random access
memory;Resource management;Software
},
durl         = {files/papers/wcet_m_ecrts15.pdf},
slides       = {files/slides/sce_wcet_m_slides.pdf}
}

@inproceedings{dantsker2014high,
title        = {
{High-Frequency Sensor Data Acquisition System (SDAC) for Flight Control
and Aerodynamic Data Collection}
},
author       = {
Dantsker, Or D. and Mancuso, Renato and Selig, Michael S. and Caccamo,
Marco
},
year         = 2014,
month        = {June},
booktitle    = {32nd AIAA Applied Aerodynamics Conference},
address      = {Atlanta, GA, USA},
doi          = {10.2514/6.2014-2565},
type         = {conference},
durl         = {files/papers/hfreq_sdac_aiaa14.pdf}
}

@inproceedings{6843715,
title        = {
{A low-power architecture for high frequency sensor acquisition in many-DOF
UAVs}
},
author       = {Mancuso, Renato and  Dantsker, Or D. and Caccamo, Marco and Selig, Michael S.},
year         = 2014,
month        = {April},
booktitle    = {
5th ACM/IEEE International Conference on Cyber-Physical Systems (ICCPS
2014)
},
address      = {Berlin, Germany},
volume       = {},
number       = {},
pages        = {103--114},
doi          = {10.1109/ICCPS.2014.6843715},
issn         = {},
type         = {conference},
abstract     = {
Unmanned Aerial Vehicles (UAVs) are becoming increasingly popular thanks to
an increase in the accessibility of components with high reliability and
reduced cost, making them suitable for civil, military and research
purposes. Vehicles classified as UAVs can have largely different properties
in terms of physical design, size, power, capabilities, as well as
associated production and operational cost. In this work, we target UAVs
that feature a high number of degrees of freedom (DOF) and that are
instrumented with a large number of sensors. For such platforms, we propose
an architecture to perform data acquisition from on-board instrumentation
at a frequency (100 Hz) that is twice as fast as existing products. Our
architecture is capable of performing acquisition with strict timing
constraints, thus, the produced data stream is suitable for performing
real-time sensor fusion. Furthermore, our architecture can be implemented
using embedded, commercial hardware, resulting in a low-cost solution.
Finally, the resulting data acquisition unit features a low-power
consumption, allowing it to operate for two to three hours with a miniature
battery.
},
keywords     = {
autonomous aerial vehicles;data acquisition;mobile robots;sensor
fusion;data stream;degrees-of-freedom;frequency 100 Hz;high frequency
sensor acquisition;low-power architecture;manyDOF UAV;miniature
battery;sensor fusion;timing constraints;unmanned aerial vehicles;Data
acquisition;Hardware;Magnetic
separation;Magnetometers;Magnetosphere;Monitoring;Pulse width modulation
},
durl         = {files/papers/sdaq_iccps14.pdf},
slides       = {files/slides/ICCPS14/}
}

@inproceedings{palloc_RTAS14,
title        = {
{PALLOC: DRAM bank-aware memory allocator for performance isolation on
multicore platforms}
},
author       = {Yun, Heechul, Mancuso, Renato and Wu, Zhen-Wei and Pellizzoni, Rodolfo},
year         = 2014,
month        = {April},
booktitle    = {
19th IEEE Real-Time and Embedded Technology and Applications Symposium
(RTAS 2014)
},
address      = {Berlin, Germany},
volume       = {},
number       = {},
pages        = {155--166},
doi          = {10.1109/RTAS.2014.6925999},
issn         = {1545-3421},
type         = {conference},
abstract     = {
DRAM consists of multiple resources called banks that can be accessed in
parallel and independently maintain state information. In Commercial
Off-The-Shelf (COTS) multicore platforms, banks are typically shared among
all cores, even though programs running on the cores do not share memory
space. In this situation, memory performance is highly unpredictable due to
contention in the shared banks. In this paper, we propose PALLOC, a DRAM
bank-aware memory allocator which exploits the page-based virtual memory
system to allocate memory pages of each application to specific banks. With
PALLOC, we can dynamically partition banks to avoid bank sharing among
cores, thereby improving isolation on COTS multicore platforms without
requiring any special hardware support. We performed an extensive set of
experiments to investigate the performance impact of DRAM bank partitioning
on two COTS multicore platforms with a set of synthetic and SPEC2006
benchmarks. Our evaluation results demonstrate that DRAM bank partitioning
significantly improves isolation and real-time performance.
},
keywords     = {
DRAM chips;paged storage;shared memory systems;COTS multicore
platforms;DRAM bank partitioning;DRAM bank-aware memory
allocator;PALLOC;commercial off-the-shelf multicore platforms;memory pages
allocation;memory performance;memory space;page-based virtual memory
system;performance isolation;shared banks;Benchmark
testing;Hardware;Kernel;Multicore processing;Random access memory;Real-time
systems;Resource management
},
durl         = {files/papers/palloc-rtas2014.pdf}
}

@inproceedings{lightprem_RTCSA14,
title        = {
{Light-PREM: Automated software refactoring for predictable execution on
COTS embedded systems}
},
author       = {Mancuso, Renato and Dudko, Roman and Caccamo, Marco},
year         = 2014,
month        = {Aug},
booktitle    = {
20th IEEE International Conference on Embedded and Real-Time Computing
Systems and Applications (RTCSA 2014)
},
address      = {Chongqing, China},
volume       = {},
number       = {},
pages        = {1--10},
doi          = {10.1109/RTCSA.2014.6910515},
issn         = {2325-1271},
type         = {conference},
abstract     = {
As real-time embedded systems become more complex, there is the need to
build them using high performance commercial off-the-shelf (COTS)
components. However, tasks can exhibit hard to predict worst case execution
times (WCET) when executing on commodity hardware, due to contention among
shared physical resources. Past work has introduced the PRedictable
Execution Model (PREM) [1] to solve this issue, but unfortunately, the time
required to manually refactor existing code according to this model is too
high. Light-PREM proposes a novel technique that automates the refactoring
process needed to convert legacy software applications to PREM-compliant
code. The advantage of Light-PREM is twofold. On one side, it makes the
adoption of PREM more attractive from an industrial point of view, because
it significantly reduces the amount of work that is needed to generate
PREM-compliant code. On the other hand, the proposed methodology is general
enough to be used with any embedded software design. Experimental results
show that Light-PREM significantly improves the predictability of real-time
applications without requiring software engineers to gain a deep
understanding about software memory usage.
},
keywords     = {
embedded systems;software maintenance;COTS embedded systems;PREM-compliant
code;automated software refactoring process;commodity hardware;embedded
software design;high performance commercial off-the-shelf components;legacy
software applications;light-PREM;predictable execution model;real-time
embedded systems;shared physical resources;software engineers;software
memory;worst case execution time prediction;Layout;Memory
management;Predictive models;Prefetching;Real-time systems;Resource
management
},
durl         = {files/papers/lightprem_rtcsa14.pdf}
}

@inproceedings{hwsched_RTCSA14,
title        = {
{A hardware architecture to deploy complex multiprocessor scheduling
algorithms}
},
author       = {Mancuso, Renato and Srivastava, Prakalp and Chen, Deming and Caccamo, Marco},
year         = 2014,
month        = {Aug},
booktitle    = {
20th IEEE International Conference on Embedded and Real-Time Computing
Systems and Applications (RTCSA 2014)
},
address      = {Chongqing, China},
volume       = {},
number       = {},
pages        = {1--10},
doi          = {10.1109/RTCSA.2014.6910541},
issn         = {2325-1271},
type         = {conference},
abstract     = {
An increasing demand for high-performance systems has been observed in the
domain of both general purpose and real-time systems, pushing the industry
towards a pervasive transition to multi-core platforms. Unfortunately,
well-known and efficient scheduling results for single-core systems do not
scale well to the multi-core domain. This justifies the adoption of more
computationally intensive algorithms, but the complexity and computational
overhead of these algorithms impact their applicability to real OSes. We
propose an architecture to migrate the burden of multi-core scheduling to a
dedicated hardware component. We show that it is possible to mitigate the
overhead of complex algorithms, while achieving power efficiency and
optimizing processors utilization. We develop the idea of “active
monitoring” to continuously track the evolution of scheduling parameters as
tasks execute on processors. This allows reducing the gap between
implementable scheduling techniques and the ideal fluid scheduling model,
under the constraints of realistic hardware.
},
keywords     = {
computational complexity;multiprocessing systems;parallel
processing;processor scheduling;ubiquitous computing;active
monitoring;complex algorithm;complex multiprocessor scheduling
algorithms;computational complexity;computational overhead;computationally
intensive algorithm;general purpose system;hardware architecture;hardware
component;high-performance system;ideal fluid scheduling model;multicore
domain;multicore platform;pervasive transition;power efficiency;processors
utilization;real-time system;realistic hardware;scheduling
parameter;scheduling techniques;single-core system;Computer
architecture;Hardware;Monitoring;Program processors;Scheduling;Scheduling
algorithms
},
durl         = {files/papers/hwsched_rtcsa14.pdf}
}

@inproceedings{rtcm13,
title        = {{Real-time cache management framework for multi-core architectures}},
author       = {Mancuso, Renato and Dudko, Roman and Betti, Emiliano and Cesati, Marco and Caccamo, Marco and Pellizzoni, Rodolfo},
year         = 2013,
month        = {April},
booktitle    = {
19th IEEE Real-Time and Embedded Technology and Applications Symposium
(RTAS 2013)
},
address      = {Philadelphia, PA, USA},
volume       = {},
number       = {},
pages        = {45--54},
doi          = {10.1109/RTAS.2013.6531078},
issn         = {1080-1812},
type         = {conference},
abstract     = {
Multi-core architectures are shaking the fundamental assumption that in
real-time systems the WCET, used to analyze the schedulability of the
complete system, is calculated on individual tasks. This is not even true
in an approximate sense in a modern multi-core chip, due to interference
caused by hardware resource sharing. In this work we propose (1) a complete
framework to analyze and profile task memory access patterns and (2) a
novel kernel-level cache management technique to enforce an efficient and
deterministic cache allocation of the most frequently accessed memory
areas. In this way, we provide a powerful tool to address one of the main
sources of interference in a system where the last level of cache is shared
among two or more CPUs. The technique has been implemented on commercial
hardware and our evaluations show that it can be used to significantly
improve the predictability of a given set of critical tasks.
},
keywords     = {
cache storage;microprocessor chips;multiprocessing systems;parallel
architectures;CPU;WCET;hardware resource sharing;kernel-level cache
management technique;multicore architectures;multicore chip;real-time cache
management framework;task memory access
patterns;Hardware;Instruments;Interference;Kernel;Memory
management;Real-time systems;Resource management
},
remark       = {Best Student Paper Award},
durl         = {files/papers/rtcm_rtas13.pdf}
}

@inproceedings{6614242,
title        = {{On-chip control flow integrity check for real time embedded systems}},
author={Abad, Fardin Abdi Taghi and Woude, Joel Van Der and Lu, Yi and Bak, Stanley and Caccamo, Marco and Sha, Lui and Mancuso, Renato and Mohan, Sibin},
year         = 2013,
month        = {Aug},
booktitle    = {
1st IEEE International Conference on Cyber-Physical Systems, Networks, and
Applications (CPSNA 2013)
},
address      = {Taipei, Taiwan},
volume       = {},
number       = {},
pages        = {26--31},
doi          = {10.1109/CPSNA.2013.6614242},
issn         = {},
type         = {conference},
abstract     = {
Modern industrial plants, vehicles and other cyber-physical systems are
increasingly being built as an aggregation of embedded platforms. Together
with the soaring number of such systems and the current trends of increased
connectivity, new security concerns are emerging. Classic approaches to
security are not often suitable for embedded platforms. In this paper we
propose a hardware based approach for checking the integrity of code flow
of real-time tasks whit precisely predictable overheads that do not affect
the critical path. Specifically, we employ a hardware module to perform
control flow graph (CFG) validation at run-time of real-time component. For
this purpose, we developed a binary-based, CFG generation tool. In
addition, we also present our implementation of a CFG integrity checking
module. The proposed approach is aimed at improving real-time systems
security.
},
keywords     = {
embedded systems;flow graphs;security of data;CFG generation tool;CFG
integrity checking module;CFG validation;binary-based generation tool;code
flow;control flow graph validation;cyber-physical systems;hardware based
approach;hardware module;industrial plants;on-chip control flow integrity
check;real time embedded systems;real-time systems security;real-time
tasks;Embedded systems;Hardware;Memory management;Monitoring;Program
processors;Real-time systems;Security
},
durl         = {files/papers/cfgctrl_cpsna13.pdf}
}

@phdthesis{mancuso2017next,
title        = {{Next-generation safety-critical systems on multi-core platforms}},
author       = {Mancuso, Renato},
year         = 2017,
publisher    = {University of Illinois at Urbana-Champaign (UIUC)},
series       = {Doctoral Dissertation},
url          = {http://hdl.handle.net/2142/97399},
type         = {theses},
durl         = {
https://www.ideals.illinois.edu/bitstream/handle/2142/97399/MANCUSO-DISSERTATION-2017.pdf?sequence=1&isAllowed=y
}
}

@techreport{UKL_techrep,
doi = {10.48550/ARXIV.2206.00789},
url = {https://arxiv.org/abs/2206.00789},
author = {Raza, Ali and Unger, Thomas and Boyd, Matthew and Munson,
Eric and Sohal, Parul and Drepper, Ulrich and Jones,
Richard and de Oliveira, Daniel Bristot and Woodman,
Larry and Mancuso, Renato and Appavoo, Jonathan and
Krieger, Orran},
keywords = {Operating Systems (cs.OS), FOS: Computer and information sciences, FOS: Computer and information sciences},
title = {Integrating Unikernel Optimizations in a General Purpose OS},
publisher = {arXiv},
year = {2022},
copyright = {arXiv.org perpetual, non-exclusive license},
type={techreport},
durl={https://arxiv.org/pdf/2206.00789.pdf}
}

@techreport{akita_20,
doi = {10.48550/ARXIV.2009.09104},
url = {https://arxiv.org/abs/2009.09104},
author = {Asyabi, Esmail and Bestavros, Azer and Mancuso, Renato and West, Richard and Sharafzadeh, Erfan},
keywords = {Operating Systems (cs.OS), FOS: Computer and information sciences, FOS: Computer and information sciences},
title = {Akita: A CPU scheduler for virtualized Clouds},
publisher = {arXiv},
year = {2020},
copyright = {arXiv.org perpetual, non-exclusive license}
type={techreport}
durl={https://arxiv.org/pdf/2009.09104.pdf}
}

@techreport{bansal2019cache,
title        = {{Cache Where you Want! Reconciling Predictability and Coherent Caching}},
author       = {
Bansal, Ayoosh and Singh, Jayati and Hao, Yifan and Wen, Jen-Yang and Mancuso, Renato and Caccamo, Marco
},
year         = 2019,
month        = {Sept},
publisher    = {University of Illinois at Urbana-Champaign (UIUC)},
address      = {Urbana, IL, USA},
url          = {https://arxiv.org/abs/1909.05349},
eprint       = {1909.05349},
archiveprefix = {arXiv},
primaryclass = {cs.DC},
type         = {techreport},
durl         = {https://arxiv.org/pdf/1909.05349}
}

@techreport{koch2019neuroflight,
title        = {{Neuroflight: Next Generation Flight Control Firmware}},
author       = {Koch, William and Mancuso, Renato and Bestavros, Azer},
year         = 2019,
month        = {Sept},
publisher    = {Boston University (BU)},
address      = {Boston, MA, USA},
url          = {https://arxiv.org/abs/1901.06553},
eprint       = {1901.06553},
archiveprefix = {arXiv},
primaryclass = {cs.RO},
type         = {techreport},
durl         = {https://arxiv.org/pdf/1901.06553}
}

@techreport{SPM_Stream_Techrep,
title        = {
{Tech Report: A Virtualized Scratchpad-Based Architecture for Real-time
Event-Triggered Applications}
},
author       = {
Gracioli, Giovani and Tabish, Rohan and Mirosanlou, Reza and Mancuso, Renato and Pellizzoni, Rodolfo and Caccamo, Marco
},
year         = 2019,
publisher    = {Technical University of Munich (TUM)},
address      = {Munich, Germany},
url          = {https://mediatum.ub.tum.de/1475015},
type         = {techreport},
durl         = {https://mediatum.ub.tum.de/doc/1475015/1475015.pdf}
}

@article{RL-attitude,
title        = {{Reinforcement Learning for UAV Attitude Control}},
author       = {Koch, William and Mancuso, Renato and West, Richard and Bestavros, Azer},
year         = 2018,
month        = {April},
journal      = {CoRR},
publisher    = {Boston University (BU)},
address      = {Boston, MA, USA},
url          = {http://arxiv.org/abs/1804.04154},
archiveprefix = {arXiv},
eprint       = {1804.04154},
timestamp    = {Tue, 01 May 2018 19:46:29 +0200},
biburl       = {https://dblp.org/rec/bib/journals/corr/abs-1804-04154},
bibsource    = {dblp computer science bibliography, https://dblp.org},
type         = {techreport},
durl         = {https://arxiv.org/pdf/1804.04154}
}

@techreport{farshchi2017deterministic,
title        = {
{Deterministic Memory Abstraction and Supporting Cache Architecture for
Real-Time Systems}
},
author       = {
Farshchi, Farzad and Valsan, Prathap Kumar and Mancuso, Renato and Yun,
Heechul
},
year         = 2017,
month        = {Oct},
journal      = {arXiv preprint arXiv:1707.05260},
publisher    = {University of Kansas (KU)},
address      = {Lawrence, KS, USA},
url          = {https://arxiv.org/abs/1707.05260},
type         = {techreport},
durl         = {https://arxiv.org/pdf/1707.05260}
}

@techreport{abdi2017achieving,
title        = {{Achieving system-level fault-tolerance with controlled resets}},
author       = {Abdi, Fardin A. T. and Mancuso, Renato and Tabish, Rohan and Caccamo, Marco},
year         = 2017,
publisher    = {University of Illinois at Urbana-Champaign (UIUC)},
address      = {Urbana, IL, USA},
type         = {techreport}
}

@misc{abdi2015techrep,
title        = {
{Reset-Based Recovery for Real-Time Cyber-Physical Systems with Temporal
Safety Constraints}
},
author       = {Abdi, Fardin and Bak, Stanley and Mancuso, Renato and Dantsker, Or D. and Caccamo, Marco},
year         = 2015,
publisher    = {University of Illinois at Urbana-Champaign (UIUC)},
address      = {Urbana, IL, USA},
type         = {techreport}
}

@techreport{melani2015resource,
title        = {{Resource Speed Optimization for Two-Stage Flow-Shop Scheduling}},
author       = {
Melani, Alessandra and Mancuso, Renato and Cullina, Daniel and Caccamo,
Marco and Thiele, Lothar
},
year         = 2015,
month        = {Nov},
publisher    = {University of Illinois at Urbana-Champaign (UIUC)},
address      = {Urbana, IL, USA},
url          = {http://hdl.handle.net/2142/88404},
type         = {techreport}
}

@techreport{mancuso2015improving,
title        = {
{Improving bandwidth utilization with deterministic delivery guarantees in
AFDX through traffic phase-shifting}
},
author       = {Mancuso, Renato and Louis, Andrew V and Caccamo, Marco},
year         = 2015,
month        = {Oct},
publisher    = {University of Illinois at Urbana-Champaign (UIUC)},
address      = {Urbana, IL, USA},
url          = {http://hdl.handle.net/2142/78193},
type         = {techreport}
}

@techreport{cesati2015madt,
title        = {{MadT: A memory access detection tool for symbolic memory profiling}},
author       = {Cesati, Marco and Mancuso, Renato and Betti, Emiliano and Caccamo, Marco},
year         = 2015,
month        = {June},
publisher    = {University of Illinois at Urbana-Champaign (UIUC)},
address      = {Urbana, IL, USA},
url          = {http://hdl.handle.net/2142/78093},
type         = {techreport}
}

@techreport{sha2014single,
title        = {
{Single core equivalent virtual machines for hard real—time computing on
multicore processors}
},
author       = {
Sha, Lui and Caccamo, Marco and Mancuso, Renato and Kim, Jung-Eun and Yoon,
Man-Ki and Pellizzoni, Rodolfo and Yun, Heechul and Kegley, Russel and
Perlman, Dennis and Arundale, Greg},
year         = 2014,
month        = {Nov},
publisher    = {University of Illinois at Urbana-Champaign (UIUC)},
address      = {Urbana, IL, USA},
url          = {http://hdl.handle.net/2142/55672},
type         = {techreport}
}

@techreport{mancuso2014response,
title        = {{Response-Time Analysis for Single Core Equivalence Framework}},
author       = {
Mancuso, Renato and Pellizzoni, Rodolfo and Caccamo, Marco and Sha, Lui and
Yun, Heechul
},
year         = 2014,
month        = {Oct},
publisher    = {University of Illinois at Urbana-Champaign (UIUC)},
address      = {Urbana, IL, USA},
url          = {http://hdl.handle.net/2142/55570},
type         = {techreport}
}